Variability-Aware Asynchronous Scheme for Optimal-Performance Delay Matching
A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
1 . A method for optimizing performance of a synthesized controller based on timing constraints specified as a set of inequalities and a cost function comprising:
synthesizing a controller wherein said controller includes at least one control input, at least one control output signal, and at least one clocking signal output;
defining at least L independent delay variables, wherein each said independent delay is independently controllable, wherein at least one independent delay variable is included in a path through said output signal, and at least one independent delay variable is included in a path through said request input signal;
defining a set of at least M constraint inequalities;
relating each of said M constraint inequalities to at least one of the L independent delays;
defining a cost function expressed using at least one of the L independent delay variables;
solving for the at least L independent delay variables using the set of M inequalities,
using the L independent delay variables and optimizing based on the cost function; and
storing said resulting M constraint inequalities in a computer-readable format.
2 . The method of claim 1 , wherein said at least L independent delay variables include at least two of, an input delay, an output delay, a clocking signal output delay.
3 . The method of claim 1 , wherein said at least M constraint inequalities includes at least one of, a linear inequality, a non-linear inequality.
4 . The method of claim 1 , wherein said cost function expresses a minimum of at least one of, a clock period, a toggling metric, an area, a latency, a frequency, a throughput metric.
5 . A method for optimizing performance of a synthesized controller based on timing constraints specified as a set of inequalities and a cost function comprising:
synthesizing a structural representation of the controller wherein said controller includes at least one request input signal, at least one request output signal, at least one acknowledge input signal, at least one acknowledge output signal and at least one clocking signal outputs;
defining at least L independent delay variables, wherein each said independent delay is independently controllable, wherein at least one independent delay variable is included in a path through said acknowledge output signal, and at least one independent delay variable is included in a path through said request input signal;
defining a set of at least M constraint inequalities, from among a master setup time constraint, a master hold time constraint, a slave setup time constraint, a slave hold time constraint, a master pulse width constraint, and a slave pulse width constraint;
relating each of said M constraint inequalities to at least one of the L independent delays;
defining a cycle period inequality to model the cycle period of said control circuit, wherein said cycle period is expressed using at least one of said L independent delay variables;
defining a cost function expressed using at least one of the L independent delay variables;
solving for the at least L independent delay variables using the set of M inequalities, using the L independent delay variables and optimizing based on the cost function; and
storing said resulting M constraint inequalities and in a computer-readable format.
6 . The method of claim 5 , wherein said at least L independent delay variables include at least two of, a request input delay, an acknowledge output delay, a master slave clock delay, a slave latch delay, a master pulse width delay, a slave pulse width delay.
7 . The method of claim 5 , wherein said at least M constraint inequalities are linear inequalities.
8 . The method of claim 5 , wherein said at least M constraint inequalities are non-linear inequalities.
9 . The method of claim 5 , wherein said cost function expresses a minimum of at least one of, a clock period, a toggling metric, an area, a latency, a frequency, a throughput metric.
10 . The method of claim 5 , wherein said solving includes using at least one of, a linear programming technique, a mathematical programming technique, a LaGrange multiplier.
11 . The method of claim 5 , wherein said L independent delay variables are each expressed as a minimum delay and a maximum delay.
12 . The method of claim 11 , wherein said solving includes solving using only minimum delays.
13 . The method of claim 11 , wherein said solving includes solving using only maximum delays.
14 . A computer program product embodied in a tangible computer readable medium for optimizing performance of a synthesized controller based on timing constraints specified as a set of inequalities and a cost function comprising:
computer code for synthesizing a controller wherein said controller includes at least one control input, at least one control output signal, and at least one clocking signal output;
computer code for defining at least L independent delay variables, wherein each said independent delay is independently controllable, wherein at least one independent delay variable is included in a path through said output signal, and at least one independent delay variable is included in a path through said request input signal;
computer code for defining a set of at least M constraint inequalities;
computer code for relating each of said M constraint inequalities to at least one of the L independent delays;
computer code for defining a cost function expressed using at least one of the L independent delay variables;
computer code for solving for the at least L independent delay variables using the set of M inequalities, using the L independent delay variables and optimizing based on the cost function; and
computer code for storing said resulting M constraint inequalities and in a computer-readable format.
15 . The computer program product of claim 14 , wherein said at least L independent delay variables include at least two of, an input delay, an output delay, a clocking signal output delay.
16 . The computer program product of claim 14 , wherein said at least M constraint inequalities includes at least one of, a linear inequality, a non-linear inequality.
17 . The computer program product of claim 14 , wherein said cost function expresses a minimum of at least one of, a clock period, a toggling metric, an area, a latency, a frequency, a throughput metric.
18 . The computer program product of claim 14 , wherein said solving includes using at least one of, a linear programming technique, a mathematical programming technique, a LaGrange multiplier.
19 . The computer program product of claim 14 , wherein said L independent delay variables are each expressed as a minimum delay and a maximum delay.
20 . The computer program product of claim 14 , further comprising at least one of, computer code for RTL synthesis, computer code for floorplanning, computer code for clock tree synthesis, computer code for routing, computer code for layout optimization, computer code for logic verification, computer code for physical design verification.