IP Library Patent Application 12268732
Patent Application
App. No. 12/268,732

Memory Systems and Accessing Methods

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Quick Facts
Patent No.
US None
App. No.
12/268,732
Abstract

Memory systems and accessing methods are disclosed. In one embodiment, a method of accessing a memory device includes accessing a first end of the memory device regarding a first data type, and accessing a second end of the memory device regarding a second data type.

Claims (30)

1 . A method of accessing a memory device, the method comprising:

accessing a first end of the memory device regarding a first data type; and

accessing a second end of the memory device regarding a second data type.

2 . The method according to claim 1 , wherein accessing the first end of the memory device regarding the first data type comprises storing data of at least one first data type, and wherein accessing the second end of the memory device regarding the second data type comprises storing data of at least one second data type.

3 . The method according to claim 1 , wherein accessing the first end of the memory device regarding the first data type comprises reading data of at least one first data type, and wherein accessing the second end of the memory device regarding the second data type comprises reading data of at least one second data type.

4 . The method according to claim 1 , further comprising allocating space in the memory device for the first data type and the second data type based on a plurality of thresholds that are dynamically programmable, thus modifying the space in the memory device for the first data type and the second data type dynamically.

5 . The method according to claim 4 , wherein the thresholds are defined so that a shared region disposed between the first end and the second end of the memory device may vary from about 0 to about the total depth of the memory device.

6 . The method according to claim 1 , further comprising accessing a shared region of the memory device, the shared region being disposed between the first end and the second end of the memory device.

7 . The method according to claim 6 , wherein accessing the shared region comprises storing or accessing data of the first data type and/or the second data type.

8 . The method according to claim 6 , wherein accessing the shared region comprises accessing a shared region that is dynamically configurable between the first end and the second end of the memory device.

9 . A method of accessing a memory device, the method comprising:

providing a memory device, the memory device having a first end and a second end opposite the first end and including a plurality of memory cells;

defining a first region of memory cells proximate the first end of the memory device; and

defining a second region of memory cells proximate the second end of the memory device, wherein data of a first data type is storable in memory cells in the first region of the memory device, and wherein data of a second data type is storable in memory cells in the second region of the memory device.

10 . The method according to claim 9 , further comprising defining a shared region of memory cells between the first region and the second region, wherein data of the first data type or the second data type is storable in the shared region.

11 . The method according to claim 10 , wherein the shared region provides an adjustable memory depth for data of the first data type storable proximate the first end of the memory device and for data of the second data type storable proximate the second end of the memory device.

12 . The method according to claim 9 , further comprising establishing at least one threshold proximate the first end or the second end of the memory device.

13 . The method according to claim 12 , wherein establishing the at least one threshold comprises establishing a threshold for an almost empty status, an almost full status, a refill-from-empty status, and/or a refill-from-full status of a portion of the memory device proximate the first end or the second end of the memory device.

14 . The method according to claim 12 , wherein establishing the at least one threshold comprises establishing at least one watermark in the memory device.

15 . The method according to claim 14 , wherein establishing the at least one watermark comprises configuring the at least one watermark using a register.

16 . The method according to claim 14 , wherein establishing the at least one watermark comprises dynamically establishing the at least one watermark.

17 . A memory system, comprising:

a memory device;

means for accessing a first end of the memory device regarding a first data type; and

means for accessing a second end of the memory device regarding a second data type.

18 . The memory system according to claim 17 , further comprising means for accessing a shared region of the memory device regarding the first data type or the second data type, the shared region being disposed between the first end and the second end of the memory device.

19 . The memory system according to claim 18 , wherein the memory device is adapted to store m data types, wherein the memory device is dividable into n sections, each section being adapted to store two of the data types, wherein m=2n.

20 . The memory system according to claim 19 , further comprising means for accessing a first end of each section and a second end of each section for a data type, the second end being opposite the first end of each section.

21 . The memory system according to claim 17 , wherein the memory device comprises a dynamic random access memory (DRAM), a static random access memory (SRAM), or a read only memory (ROM).

22 . A computer system including the memory system according to claim 17 , wherein the computer system includes a processor, a controller, one or more input/output ports, and/or peripheral devices coupleable to the memory system.

Assignments (7)
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045085/0292 →
MERGER Recorded Dec 18, 2017
From: LANTIQ DEUTSCHLAND GMBH
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 044907/0045 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →
GRANT OF SECURITY INTEREST IN U.S. PATENTS Recorded Nov 29, 2010
From: LANTIQ DEUTSCHLAND GMBH
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 025406/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
To: LANTIQ DEUTSCHLAND GMBH
Reel/Frame 024529/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
Reel/Frame 024483/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2008
From: KUMAR, RAVI RANJAN; PADMANABHAN, SREEKUMAR
To: INFINEON TECHNOLOGIES AG
Reel/Frame 021816/0450 →