Method for manufacturing a transistor
View Patent ↗A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.
1. A method for manufacturing a transistor comprising:
forming a photoresist pattern on a semiconductor substrate including an isolation layer;
forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask;
forming a gate oxide layer on the semiconductor substrate;
forming a poly gate on the gate oxide layer;
forming source and drain regions a predetermined distance from the poly gate; and
forming a silicide layer on the poly gate and the source and drain regions.
2. The method according to claim 1 , wherein the first dopant ions are implanted at a higher dose or density and at a lower energy than the second dopant ions.
3. The method according to claim 1 , wherein the second dopant ions are implanted at a lower dose or density and at a deeper position from the surface of the semiconductor substrate than the first dopant ions.
4. The method according to claim 1 , wherein the first dopant ions are boron ions and the second dopant ions are phosphorus ions.
5. The method according to claim 1 , further comprising forming spacers on sidewalls of the poly gate.
6. The method according to claim 1 , wherein the gate oxide layer is formed thicker on the drift region than the masked parts.
7. The method according to claim 6 , wherein a thickly formed part of the gate oxide layer performs a self-aligning function during the source and drain implantation.
8. The method according to claim 6 , wherein the length of the drift region is increased by the thick part of the gate oxide layer.
9. The method according to claim 1 , wherein forming the source and drain region comprises a double ion implantation.
10. The method according to claim 9 , wherein, in the source and drain region, a source region is formed on a drain region by double ion implantation.
11. The method according to claim 1 , wherein forming the drift region comprises a lightly doped drain (LDD) implantation using the photoresist pattern as a mask.
12. The method according to claim 1 , further comprising, after the drift region is formed, cleaning and annealing the semiconductor substrate.