Structure of high performance combo chip and processing method
View Patent ↗A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.
1. A chip package comprising:
a circuit substrate;
an array of contact balls on a first side of said circuit substrate;
a first chip over a second side of said circuit substrate, wherein said second side of said circuit substrate is opposite to said first side of said circuit substrate, wherein a horizontal distance between a left sidewall of said first chip and a right sidewall of said first chip is less than that between a left sidewall of said circuit substrate and a right sidewall of said circuit substrate, wherein said first chip comprises a silicon substrate;
multiple first metal bumps between said circuit substrate and said first chip and vertically under said first chip, wherein each of said multiple first metal bumps has a bottom end on said second side of said circuit substrate;
a first underfill between said first chip and said circuit substrate and between said multiple first metal bumps, wherein said first underfill contacts said circuit substrate;
a second chip over said first chip, wherein said second chip comprises a silicon substrate;
multiple second metal bumps between said first and second chips and vertically under said second chip, wherein each of said multiple second metal bumps has a top end on said second chip and a bottom end on said first chip; and
a second underfill between said first and second chips and between said multiple second metal bumps, wherein said second underfill contacts said first and second chips.
2. The chip package of claim 1 , wherein said circuit substrate comprises a printed circuit board.
3. The chip package of claim 1 , wherein said multiple first metal bumps comprise a solder.
4. The chip package of claim 1 , wherein said multiple second metal bumps comprise a solder.
5. The chip package of claim 1 , wherein said bottom ends of said multiple second metal bumps contact multiple first metal contact points of said first chip, and said top ends of said multiple second metal bumps contact multiple second metal contact points of said second chip.
6. The chip package of claim 1 , wherein said circuit substrate comprises multiple interconnect layers in said circuit substrate, wherein said multiple interconnect layers connect said multiple first metal bumps with said array of contact balls.
7. The chip package of claim 1 , wherein said first chip comprises a memory chip.
8. The chip package of claim 1 , wherein said first chip comprises a logic chip.
9. The chip package of claim 1 , wherein no preformed substrate is between said first chip and said multiple first metal bumps.
10. A chip package comprising:
a circuit substrate;
an array of contact balls on a first side of said circuit substrate;
a first silicon substrate over a second side of said circuit substrate, wherein said second side of said circuit substrate is opposite to said first side of said circuit substrate, wherein a horizontal distance between a left sidewall of said first silicon substrate and a right sidewall of said first silicon substrate is less than that between a left sidewall of said circuit substrate and a right sidewall of said circuit substrate;
multiple first metal bumps between said circuit substrate and said first silicon substrate and vertically under said first silicon substrate, wherein each of said multiple first metal bumps has a bottom end on said second side of said circuit substrate, wherein no preformed substrate is between said first silicon substrate and said multiple first metal bumps;
a chip over said first silicon substrate, wherein said chip comprises a second silicon substrate; and
multiple second metal bumps between said chip and said first silicon substrate and vertically under said chip, wherein each of said multiple second metal bumps has a top end on said chip, wherein no preformed substrate is between said first silicon substrate and said multiple second metal bumps.
11. The chip package of claim 10 further comprising an underfill between said circuit substrate and said first silicon substrate and between said multiple first metal bumps.
12. The chip package of claim 10 further comprising an underfill between said chip and said first silicon substrate and between said multiple second metal bumps.
13. The chip package of claim 10 , wherein said circuit substrate comprises a printed circuit board.
14. The chip package of claim 10 , wherein said multiple first metal bumps comprise a solder.
15. The chip package of claim 10 , wherein said multiple second metal bumps comprise a solder.
16. The chip package of claim 10 , wherein bottom ends of said multiple second metal bumps contact multiple first metal contact points at a side of said first silicon substrate, wherein said top ends of said multiple second metal bumps contact multiple second metal contact points of said chip, wherein said side of said first silicon substrate faces said chip.
17. The chip package of claim 10 , wherein said circuit substrate comprises multiple interconnect layers in said circuit substrate, wherein said multiple interconnect layers connect said multiple first metal bumps with said array of contact balls.
18. A chip package comprising:
a circuit substrate;
multiple contacts on a first side of said circuit substrate;
a dielectric layer over a second side of said circuit substrate, wherein said second side of said circuit substrate is opposite to said first side of said circuit substrate;
a first chip over said second side of said circuit substrate and between a left portion of said dielectric layer and a right portion of said dielectric layer, wherein said first chip comprises a silicon substrate, wherein a horizontal distance between a left sidewall of said first chip and a right sidewall of said first chip is less than that between a left sidewall of said circuit substrate and a right sidewall of said circuit substrate, wherein said left portion of said dielectric layer contacts said left sidewall of said first chip, and wherein said right portion of said dielectric layer contacts said right sidewall of said first chip;
a metal via passing vertically through said left portion of said dielectric layer;
a patterned metal layer over said second side of said circuit substrate, under said dielectric layer and under said first chip, wherein said patterned metal layer contacts a bottom end of said metal via, wherein said patterned metal layer is connected to said metal via;
a second chip comprising a first portion vertically over said first chip, wherein said second chip comprises a silicon substrate; and
a metal interconnect connecting said second chip to said first chip.
19. The chip package of claim 18 further comprising multiple metal bumps between said circuit substrate and said first chip.
20. The chip package of claim 18 , wherein said metal interconnect is between said first and second chips.
21. The chip package of claim 18 , wherein said circuit substrate comprises a printed circuit board.
22. The chip package of claim 19 , wherein said multiple metal bumps comprise a solder.
23. The chip package of claim 18 , wherein said metal interconnect comprises a solder.
24. The chip package of claim 18 , wherein said first chip comprises a memory chip.
25. The chip package of claim 18 , wherein said first chip comprises a logic chip.
26. The chip package of claim 18 , wherein said second chip further comprises a second portion overhanging said first chip.
27. A chip package comprising:
a circuit component;
an array of contact balls on a bottom side of said circuit component; and
a packaged semiconductor device over a top side of said circuit component, wherein said packaged semiconductor device joins said circuit component, wherein said packaged semiconductor device comprises a dielectric layer over said top side, a first chip over said top side and between a left portion of said dielectric layer and a right portion of said dielectric layer, wherein said first chip has a left sidewall contacting said left portion of said dielectric layer and a right sidewall contacting said right portion of said dielectric layer, a second chip having a first portion vertically over said first chip, a metal interconnect connecting said second chip to said first chip, and multiple metal bumps having multiple bottom ends on said top side.
28. The chip package of claim 27 , wherein said multiple metal bumps comprise a solder.
29. The chip package of claim 27 , wherein said metal interconnect comprises a solder.
30. The chip package of claim 27 , wherein said second chip has a second portion overhanging said first chip.
31. The chip package of claim 27 , wherein said dielectric layer has a left sidewall and a right sidewall opposite and substantially parallel to said left sidewall of said dielectric layer.
32. The chip package of claim 27 , wherein said first chip comprises a memory chip.
33. The chip package of claim 27 , wherein said multiple metal bumps are between said first chip and said top side.