BTSC pilot signal lock
View Patent ↗An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.
1. An apparatus comprising:
a phase detector to receive a reference signal at a reference frequency and a feedback signal and to detect a phase relationship between the reference signal and the feedback signal, the phase detector being clocked by a clock signal at a clock frequency which is sufficiently higher than the reference frequency to sample the reference signal to generate a phase difference signal as an output from the phase detector to indicate the phase relationship;
a digital loop filter clocked at the clock frequency to receive the phase difference signal and to filter the phase difference signal to generate an offset signal as an indication of the phase relationship between the reference signal and the feedback signal;
a phase accumulator coupled to receive a value associated with a frequency of an output signal and also coupled to receive the offset signal, in which the phase accumulator provides offset adjustments to the value setting the frequency of the output signal to generate a phase corrected signal and the feedback signal;
a sinusoid generator coupled to receive the phase corrected signal to generate an output signal that tracks to the reference signal; and
a down sampler to down sample the output signal of the sinusoid generator to generate a down-sampled signal at a frequency lower than the clock frequency, wherein the down-sampled signal is used for generating a pilot signal for a BTSC encoder circuit.
2. The apparatus of claim 1 , wherein the phase detector includes an up/down counter to count signal state changes of the reference signal and the feedback signal to detect the phase relationship between the reference signal and the feedback signal.
3. The apparatus of claim 1 , wherein the digital loop filter includes a first digital filter to determine a proportional value and a second digital filter to determine an integrator value, wherein the proportional and integrator values are combined to generate the offset signal.
4. The apparatus of claim 3 , wherein the first digital filter and the second digital filter each includes a cascade of multiple programmable stages.
5. The apparatus of claim 1 , wherein the clock frequency is an integer multiple of the frequency of the down-sampled signal.
6. The apparatus of claim 1 , wherein when the clock frequency is a non-integer multiple of the frequency of the down-sampled signal, the phase accumulator introduces a compensating value to the phase corrected signal to compensate for the non-integer multiple.
7. The apparatus of claim 1 , wherein the digital loop filter includes a saturator to limit the offset signal.
8. A method comprising:
detecting in a phase detector a phase relationship between a feedback signal and a received reference signal that is at a reference frequency, wherein the phase detector is clocked by a clock signal at a clock frequency which is sufficiently higher than the reference frequency to sample the reference signal to generate a phase difference signal as an output from the phase detector to indicate the phase relationship;
filtering at the clock frequency the phase difference signal to generate an offset signal as an indication of the phase relationship between the reference signal and the feedback signal;
generating an offset adjustment to a value associated with a frequency of an output signal based on the offset signal to generate a phase corrected signal and the feedback signal;
generating an output signal that tracks to the reference signal based on the phase collected signal; and
down sampling the output signal to generate a down-sampled signal at a frequency lower than the clock frequency, wherein the down-sampled signal is used for generating a pilot signal for a BTSC encoder circuit.
9. The method of claim 8 , wherein the detecting includes using an up/down counter to count signal state changes of the reference signal and the feedback signal to detect the phase relationship between the reference signal and the feedback signal.
10. The method of claim 8 , wherein the filtering includes filtering to determine a proportional value and filtering to determine an integrator value, wherein the proportional and integrator values are combined to generate the offset signal.
11. The method of claim 8 , wherein the filtering includes use of a cascade of multiple programmable stages in a digital filter.
12. The method of claim 8 , wherein the clock frequency is an integer multiple of the frequency of the down-sampled signal.
13. The method of claim 8 , wherein when the clock frequency is a non-integer multiple of the frequency of the down-sampled signal, the phase corrected signal includes a compensating value to compensate for the non-integer multiple.
14. The method of claim 8 , wherein the filtering includes a saturator to limit the offset signal.