Array substrate and method of manufacturing the same
View Patent ↗A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
1. An array substrate comprising:
a base substrate having a pixel area;
a gate line including a first seed layer formed on the base substrate and a first metal layer formed on the first seed layer;
a first insulation layer formed on the base substrate having the gate line;
a second insulation layer formed on the base substrate having the first insulation layer, wherein a line trench is formed through the second insulation layer in a direction crossing the gate line;
a data line including a second seed layer formed below the line trench and a second metal layer formed in the line trench; and
a pixel electrode formed in the pixel area.
2. The array substrate of claim 1 , wherein the first insulation layer comprising an organic insulation layer having a low permittivity.
3. The array substrate of claim 1 , wherein the base substrate has a trench formed thereon, and
the first seed layer and the first metal layer are formed in the trench of the substrate.
4. The array substrate of claim 1 , further comprising a switching element electrically connected to the gate line, the data line and the pixel electrode.
5. The array substrate of claim 4 , wherein the switching element comprises a gate electrode including the first seed layer and the first metal layer, a source electrode including the second seed layer, and a drain electrode including the second seed layer, and
the drain electrode and the pixel electrode are electrically connected to the second metal layer formed on the drain electrode.
6. The array substrate of claim 1 , further comprising:
a gate pad part formed at an edge portion of the gate line; and
a data pad part formed at an edge portion of the data line,
wherein the gate pad part comprises the first seed layer, the first metal layer formed on the first seed layer, a second metal layer formed in correspondence with a gate pad hole formed through the second insulation layer, and a gate pad electrode contacting with the second metal layer, and
the data pad part comprises the second seed layer, the second metal layer formed in correspondence with a data pad hole formed through the second insulation layer, and a data pad electrode contact with the second seed layer.
7. The array substrate of claim 1 , wherein the second insulation layer is an organic layer.
8. The array substrate of claim 7 , further comprising:
a light-blocking layer formed on the second insulation layer in correspondence with the gate line and the data line; and
a color filter layer formed between the second insulation layer and the pixel electrode.
9. The array substrate of claim 8 , further comprising a capping layer formed on the light-blocking layer and the color filter layer.
10. The array substrate of claim 1 , wherein the second insulation layer and the color filter layer formed in the pixel area are formed from a same material.
11. The array substrate of claim 10 , further comprising a capping layer formed on the second insulation layer.
12. The array substrate of claim 1 , further comprising an organic layer formed on the base substrate to have a trench formed thereon,
wherein the first seed layer and the first metal layer are formed in the trench.