IP Library Granted Patent US 8,421,072
Granted Patent B2
US 8,421,072 · App. 12/269,851 · Granted Apr 16, 2013

Electronic device having thermally managed electron path and method of thermal management of very cold electrons

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Quick Facts
Patent No.
US 8,421,072
App. No.
12/269,851
Granted
Apr 16, 2013
Kind
B2
Abstract

A device and a method of thermal management. In one embodiment, the device includes an integrated circuit, including: (1) a conductive region configured to be connected to a voltage source, (2) a transistor having a semiconductor channel with a controllable conductivity and (3) first and second conducting leads connecting to respective first and second ends of said channel, wherein a charge in the conductive region is configured to substantially raise an electrical potential energy of conduction charge carriers in the semiconductor channel and portions of said leads are located where an electric field produced by said charge is substantially weaker than near the semiconductor channel.

Claims (18)

1. An apparatus, comprising:

an integrated circuit, including:

a conductive region configured to be connected across a voltage,

a transistor having a semiconductor channel with a controllable conductivity; and

a first conducting lead and a second conducting lead connecting to respective first and second ends of said channel; and

wherein the conductive region is configured store a charge to substantially raise an electrical potential energy of conduction charge carriers in the semiconductor channel, portions of the first conducting lead and the second conducting lead being located where an electric field produced by said charge is substantially weaker than near the semiconductor channel, and

the channel includes a first tunnel junction capable of passing the conduction charge carriers from the first conducting lead to a quantum island and a second tunnel junction capable of passing the conduction charge carriers from the quantum island to the second conducting lead.

2. The apparatus of claim 1 , further comprising a DC voltage source connected across the conductive region with a polarity that raises the electrical potential energy of the conduction charge carriers in the semiconductor channel with respect to the electrical potential energy of said conduction charge carriers therein in an absence of the DC voltage source.

3. The apparatus of claim 1 , wherein the semiconductor channel is located next to the conductive region.

4. The apparatus of claim 1 , further comprising a cooling system configured to cool said integrated circuit to below 150° Kelvin without using cryogenic liquids and wherein a voltage source providing the voltage is configured to further reduce an absolute temperature of the conduction charge carriers in the semiconductor channel by at least 10 percent.

5. The apparatus of claim 4 , wherein the voltage source is configured to further reduce an absolute temperature of the conduction charge carriers in the semiconductor channel by at least 20 percent.

6. The apparatus of claim 1 , further comprising a cooling system configured to cool said integrated circuit to below 0.5° Kelvin and wherein a voltage source providing the voltage is configured to further reduce an absolute temperature of the conduction charge carriers in the semiconductor channel by at least 5 percent.

7. The apparatus of claim 1 further comprising a cooling system configured to cool said integrated circuit to below 0.3° Kelvin and wherein a voltage source providing the voltage is configured to further reduce an absolute temperature of the conduction charge carriers in the semiconductor channel by at least 5 percent.

8. The apparatus of claim 1 , further comprising a cooling system configured to cool said integrated circuit to below 0.03° Kelvin and wherein a voltage source providing the voltage is configured to further reduce an absolute temperature of the conduction charge carriers in the semiconductor channel by at least 5 percent.

9. The apparatus of claim 1 , wherein the transistor is a single electron transistor.

10. The apparatus of claim 1 , wherein the transistor is connected to operate as a sensor of a thermometer or a microwave detector.

11. The apparatus of claim 1 , further comprising conducting leads connected ends of the semiconductor channel, substantial portions of the leads being located in a region where an electric field generated by the charge is substantially weaker than near the semiconductor channel.

12. The apparatus of claim 1 , wherein the voltage reduces an absolute temperature of the conduction charge carriers in the semiconductor channel.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Jun 3, 2021
From: TERRIER SSC, LLC
To: WSOU INVESTMENTS, LLC
Reel/Frame 056526/0093 →
SECURITY INTEREST Recorded Jun 1, 2021
From: WSOU INVESTMENTS, LLC
To: OT WSOU TERRIER HOLDINGS, LLC
Reel/Frame 056990/0081 →
RELEASE OF SECURITY INTEREST Recorded May 21, 2019
From: OCO OPPORTUNITIES MASTER FUND, L.P. (F/K/A OMEGA CREDIT OPPORTUNITIES MASTER FUND LP
To: WSOU INVESTMENTS, LLC
Reel/Frame 049246/0405 →
SECURITY INTEREST Recorded May 20, 2019
From: WSOU INVESTMENTS, LLC
To: BP FUNDING TRUST, SERIES SPL-VI
Reel/Frame 049235/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2017
From: ALCATEL LUCENT
To: WSOU INVESTMENTS, LLC
Reel/Frame 044000/0053 →
SECURITY INTEREST Recorded Sep 21, 2017
From: WSOU INVESTMENTS, LLC
To: OMEGA CREDIT OPPORTUNITIES MASTER FUND, LP
Reel/Frame 043966/0574 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2014
From: CREDIT SUISSE AG
To: ALCATEL-LUCENT USA INC.
Reel/Frame 033949/0016 →
SECURITY INTEREST Recorded Mar 7, 2013
From: ALCATEL-LUCENT USA INC.
To: CREDIT SUISSE AG
Reel/Frame 030510/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2013
From: ALCATEL-LUCENT USA INC.
To: ALCATEL LUCENT
Reel/Frame 029823/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2008
From: SIMON, STEVEN H.
To: ALCATEL-LUCENT USA INC.
Reel/Frame 021825/0796 →