Flash memory and method for manufacturing the same
View Patent ↗Provided are a flash memory and a method for manufacturing the same. The flash memory includes a semiconductor substrate having a device isolation region and an active region; a stacked gate on the semiconductor substrate; an insulation layer covering the semiconductor substrate and the stacked gate; a drain contact penetrating the insulation layer on one side of the stacked gate; and a source line penetrating the insulation layer on an opposite side of the stacked gate.
1. A flash memory comprising:
a semiconductor substrate including a device isolation region and an active region;
a stack gate on the active region, the stack gate comprising a gate insulation layer formed on the semiconductor substrate, a floating gate formed on the gate insulation layer, a dielectric layer formed on the floating gate, and a control gate formed on the dielectric layer;
a drain terminal on one side of the stack gate;
a source terminal on an opposite side of the stack gate;
an insulation layer covering the semiconductor substrate and the stack gate;
a drain contact penetrating the insulation layer on the one side of the stack gate, the drain contact making electrical contact with only the drain terminal;
a source line penetrating the insulation layer on the opposite side of the stack gate, the source line interconnecting source terminals of adjacent stack gates; and
a source line contact on the source line, wherein the drain contact and the source line consist essentially of identical materials.
2. The flash memory according to claim 1 , further comprising a silicide formed on a top and on the drain terminal.
3. The flash memory according to claim 1 , further comprising:
a spacer on a sidewall of the stack gate; and
a salicide on a top and on the drain terminal.
4. The flash memory according to claim 1 , further comprising a barrier dielectric layer separating the stack gate and the insulation layer.
5. The flash memory according to claim 4 , wherein the barrier dielectric layer comprises a nitride layer.
6. The flash memory according to claim 1 , wherein the source line contacts one of the plurality of device isolation regions between adjacent active regions.
7. The flash memory according to claim 6 , wherein the source line is formed on the semiconductor substrate and the device isolation region.
8. The flash memory according to claim 6 , wherein the source line extends to a top surface of the insulation layer.
9. A flash memory comprising:
a semiconductor substrate including a plurality of device isolation regions and a plurality of active regions;
a plurality of stack gates on each of the plurality of active regions, each of the plurality of stack gates comprising a gate insulation layer on the semiconductor substrate, a floating gate on the gate insulation layer, a dielectric layer on the floating gate, and a control gate on the dielectric layer;
a drain terminal on one side of each of the plurality of stack gates in each of the active regions;
a common source terminal between adjacent ones of the plurality of stack gates;
an insulation layer covering the semiconductor substrate and each of the plurality of stack gates;
a plurality of drain contacts penetrating the insulation layer on the one side of each of the plurality of stack gates, each of the plurality of drain contacts making electrical contact with only one of the plurality of drain terminals;
a source line penetrating the insulation layer between said adjacent ones of the plurality of stack gates, the source line interconnecting the common source terminals in adjacent active regions; and
a source line contact on the source line, wherein each of the plurality of drain contacts and the source line consist essentially of identical materials.
10. The flash memory according to claim 9 , further comprising a silicide on a top of each of the plurality of stack gates and on each of the drain terminals.
11. The flash memory according to claim 9 , further comprising:
a spacer on a sidewall of each of the plurality of stack gates; and
a salicide on a top of each of the plurality of stack gates and on each of the drain terminals.
12. The flash memory according to claim 9 , further comprising a barrier dielectric layer separating the plurality of stack gates and the insulation layer.
13. The flash memory according to claim 12 , wherein the barrier dielectric layer comprises a nitride layer.
14. The flash memory according to claim 9 , wherein the source line contacts one of the plurality of device isolation regions between the adjacent active regions.
15. The flash memory according to claim 14 , wherein the source line extends to a top surface of the insulation layer.
16. The flash memory of claim 13 , wherein the insulation layer comprises a silicon oxide layer.
17. The flash memory of claim 1 , wherein the drain contact and the source line comprise tungsten.
18. The flash memory of claim 17 , wherein the drain contact and the source line further comprise an adhesion layer and/or diffusion barrier layer.
19. The flash memory of claim 9 , wherein each of the plurality of drain contacts and the source line comprise tungsten.
20. The flash memory of claim 19 , wherein each of the plurality of drain contacts and the source line further comprise an adhesion layer and/or diffusion barrier layer.