IP Library Granted Patent US 8,053,286
Granted Patent B2
US 8,053,286 · App. 12/270,875 · Granted Nov 8, 2011

Method of forming semiconductor device including trench gate structure

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Quick Facts
Patent No.
US 8,053,286
App. No.
12/270,875
Granted
Nov 8, 2011
Kind
B2
Abstract

A method of forming a semiconductor device is provided, which may include, but is not limited to, the following processes. Grooves may be formed in an insulating region and in a semiconductor region, while forming burrs near the boundary between the insulating region and the semiconductor region. Protection films may be selectively formed on inside walls of the grooves except on bottom walls of the grooves. A selective thermal process may be carried out in the presence of the protection films, thereby removing the burrs.

Claims (38)

1. A method of forming a semiconductor device, comprising:

forming grooves in an insulating region and in a semiconductor region, with forming burrs near the boundary between the insulating region and the semiconductor region;

selectively forming protection films on inside walls of the grooves except on bottom walls of the grooves; and

carrying out a selective thermal process in the presence of the protection films, thereby removing the burrs,

wherein selectively forming the protection films comprises:

forming the protection film on the side and bottom walls of the grooves;

carrying out an anisotropic etching process for etching the protection film, so that the protection film on the side walls of the groove is thicker than the protection film at the bottoms of the groove; and

carrying out an isotropic etching process for etching the protection film, so that the protection film is removed from the bottoms of the grooves, while the protection film resides on the side walls of the grooves.

2. The method according to claim 1 , wherein carrying out the selective thermal process comprises carrying out a hydrogen baking process.

3. The method according to claim 1 , wherein carrying out the selective thermal process is carried out to cause selective migration of semiconductor on the bottom walls of the grooves.

4. The method according to claim 1 , wherein the selective thermal process is carried out to recover damages that have been introduced into the semiconductor substrate when the grooves have been formed.

5. The method according to claim 1 , wherein the selective thermal process is carried out to avoid any substantive deformation of the grooves.

6. The method according to claim 1 , wherein the isotropic etching process is a chemical etching process.

7. The method according to claim 1 , wherein forming the protection film comprises: a low pressure chemical vapor deposition process for forming a high temperature oxide film.

8. A method of forming a semiconductor device, comprising:

forming grooves in an insulating region and in a semiconductor region, with forming burrs near the boundary between the insulating region and the semiconductor region;

selectively forming protection films on inside walls of the grooves except on bottom walls of the grooves; and

carrying out a selective hydrogen baking process in the presence of the protection films, thereby removing the burrs and recovering damages that have been introduced into the semiconductor substrate when the grooves have been formed,

wherein selectively forming the protection films comprises:

forming the protection film on the side and bottom walls of the grooves;

carrying out an anisotropic etching process for etching the protection film, so that the protection film on the side walls of the groove is thicker than the protection film at the bottoms of the groove; and

carrying out an isotropic etching process for etching the protection film, so that the protection film is removed from the bottoms of the grooves, while the protection film resides on the side walls of the grooves.

9. The method according to claim 8 , wherein carrying out the selective thermal process is carried out to cause selective migration of semiconductor on the bottom walls of the grooves.

10. The method according to claim 8 , wherein the selective thermal process is carried out to avoid any substantive deformation of the grooves.

11. The method according to claim 8 , wherein the isotropic etching process is a chemical etching process.

12. The method according to claim 8 , wherein forming the protection film comprises: a low pressure chemical vapor deposition process for forming a high temperature oxide film.

13. A method of forming a semiconductor device, comprising:

forming grooves in an insulating region and in a semiconductor region;

selectively forming protection films on inside walls of the grooves except on bottom walls of the grooves; and

causing selective migration of semiconductor on the bottom walls of the grooves in the presence of the protection films,

wherein selectively forming the protection films comprises:

forming the protection film on the side and bottom walls of the grooves;

carrying out an anisotropic etching process for etching the protection film, so that the protection film on the side walls of the groove is thicker than the protection film at the bottoms of the groove; and

carrying out an isotropic etching process for etching the protection film, so that the protection film is removed from the bottoms of the grooves, while the protection film resides on the side walls of the grooves.

14. The method according to claim 13 , wherein the grooves are formed, while burrs are formed near the boundary between the insulating region and the semiconductor region, and wherein the burrs are removed by the selective migration.

15. The method according to claim 13 , wherein carrying out the selective thermal process comprises carrying out a hydrogen baking process.

16. The method according to claim 13 , wherein the isotropic etching process is a chemical etching process.

17. The method according to claim 13 , wherein forming the protection film comprises: a low pressure chemical vapor deposition process for forming a high temperature oxide film.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032896/0209 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2008
From: MIYATA, KYOKO; AISO, FUMIKI
To: ELPIDA MEMORY, INC.
Reel/Frame 021832/0929 →