Light emitting device methods
Light-emitting device methods are disclosed.
1. A method of making a light emitting device, the method comprising:
providing a first multi-layer stack, comprising:
a substrate;
a submount, and
a semiconductor layer between the substrate and the submount, the semiconductor layer being supported by the submount wherein the semiconductor layer and submount are selected so that a coefficient of thermal expansion of the submount differs from a coefficient of thermal expansion of the semiconductor layer by less than about 15%;
removing, at least partially, the semiconductor layer; and
removing the substrate from the first multi-layer stack to form a second multi-layer stack.
2. The method of claim 1 , wherein the thermal expansion of the submount differs from the coefficient of thermal expansion of the semiconductor layer by less than about 10%.
3. The method of claim 1 , wherein the coefficient of thermal expansion of the submount differs from the coefficient of thermal expansion of the semiconductor layer by less than about 5%.
4. The method of claim 1 , wherein a thickness of the submount is greater than a thickness of the substrate.
5. The method of claim 1 , wherein the submount is at least about 10 microns thick.
6. The method of claim 1 , wherein the submount is at most about five millimeters thick.
7. The method of claim 1 , wherein the substrate is at most about one millimeter thick.
8. The method of claim 1 , wherein the submount has a cross-sectional area of at least about four inches.
9. The method of claim 1 , wherein the semiconductor layer comprises a III-V semiconductor layer.
10. The method of claim 9 , wherein the III-V semiconductor layer comprises a nitride.
11. The method of claim 9 , wherein the III-V semiconductor layer comprises a gallium nitride compound.
12. The method of claim 1 , wherein the submount comprises a material selected from the group consisting of germanium, silicon, silicon-carbide, copper, copper-tungsten, diamond, nickel-cobalt, and combinations thereof.
13. The method of claim 12 , wherein the submount is copper-tungsten.
14. The method of claim 1 , wherein the multi-layer stack includes a quantum well-containing region.
15. The method of claim 1 , wherein the semiconductor layer is a buffer layer.
16. The method of claim 1 , wherein removing the semiconductor layer exposes a surface of an n-doped semiconductor layer.
17. The method of claim 1 , wherein removing the substrate from the first multi-layer stack results in formation of a residue on a surface of the buffer layer.
18. The method of claim 16 , further comprising forming a dielectric function that varies spatially according to a pattern in the exposed surface of the n-doped semiconductor layer.
19. The method of claim 16 , further comprising roughening the exposed surface of the n-doped semiconductor layer.
20. The method of claim 1 , wherein the second multi-layer stack includes a bonding layer comprising a gold-tin alloy.