Granted Patent B2

US 8,095,831 · App. 12/273,155 · Granted Jan 10, 2012

Abstract

Claims (30)

1. A data processing system, comprising:

a processor;

a cache coupled to the processor; and

cache control circuitry coupled to the cache, the cache control circuitry performing error detection, the cache control circuitry further comprising a user programmable error action control register for storing a control value for selecting one of a plurality of error actions to be taken when a cache error is detected, wherein a first value of the control value selected by a user implements an automatic invalidation of a cache line containing the cache error without an exception being taken regardless of whether the cache line is dirty or clean, and a second value of the control value selected by the user implements an automatic invalidation of a cache line containing the cache error with an exception being taken regardless of whether the cache line is dirty or clean, wherein the user dynamically programs the control value which determines whether error action to be taken is a transparent operation or a non-transparent operation.

2. The data processing system of claim 1 wherein a third value of the control value within the user programmable error action control register generates an exception without modifying contents of the cache, the exception permitting logging of the detected error and examination of stored information within the cache to gather information about the detected error.

3. The data processing system of claim 1 wherein a third value of the control value within the user programmable error action control register implements automatic correction of the detected error without invalidation of information associated with the detected error and without generating an exception.

4. The data processing system of claim 1 wherein a third value of the control value within the user programmable error action control register implements automatic correction of the detected error and generates an exception, wherein the cache control circuitry implements automatic correction by performing an error correction code (ECC) operation on the cache line containing the cache error to correct the cache error and outputting the corrected cache line from the cache.

5. The data processing system of claim 4 wherein a fourth value of the control value within the user programmable error action control register implements an automatic invalidation of the cache line containing the cache error if the cache line is a clean cache line, and if the cache line is a dirty cache line an exception is generated and the cache line is left unaltered such that the cache line is not invalidated.

6. The data processing system of claim 5 wherein a fifth value of the control value within the user programmable error action control register implements automatic correction of the detected error without invalidation of information associated with the detected error and without generating an exception, wherein the cache control circuitry implements automatic correction by performing an error correction code (ECC) operation on the cache line containing the cache error to correct the cache error and outputting the corrected cache line from the cache.

7. The data processing system of claim 1 wherein when the control value is set to the first value during a first portion of a time interval a first portion of an application is executed with transparency of cache errors to the processor, and when the control value is set to the second value during a second portion of the time interval wherein a second portion of the application is executed with cache errors being visible to the processor.

8. The data processing system of claim 1 wherein a third value of the control value within the user programmable error action control register implements an automatic invalidation of the cache line containing the cache error if the cache line is a clean cache line, and if the cache line is a dirty cache line an exception is generated and the cache line is left unaltered such that the cache line is not invalidated.

9. The data processing system of claim 1 wherein the user programmable error action control register further comprises a second control value, the second control value controlling enablement of the error detection of the cache control circuitry.

10. The data processing system of claim 1 , wherein when the control value has the second value, a current instruction being executed is suppressed and after automatic invalidation of the cache line and after processing the taken exception, the current instruction that was suppressed is re-executed.

11. A method comprising:

coupling a processor to a cache;

coupling cache control circuitry to the cache for performing error detection of information within the cache; and

coupling a user programmable error action control register to the cache control circuitry, the user programmable error action control register storing a control value for selecting one of a plurality of error actions to be taken when a cache error is detected, wherein a first value of the control value selected by a user implements an automatic invalidation of a cache line containing the cache error without an exception being taken regardless of whether the cache line is dirty or clean, and a second value of the control value selected by the user implements an automatic invalidation of a cache line containing the cache error with an exception being taken regardless of whether the cache line is dirty or clean, wherein the user dynamically programs the control value which determines whether error action to be taken is a transparent operation or a non-transparent operation.

12. The method of claim 11 further comprising:

assigning a third value of the control value within the user programmable error action control register to generate an exception without modifying contents of the cache, the exception permitting logging of the detected error and examination of stored information within the cache to gather information about the detected error.

13. The method of claim 11 further comprising:

assigning a third value of the control value within the user programmable error action control register to implement automatic correction of the detected error without invalidation of information associated with the detected error and without generating an exception, wherein implementing the automatic correction comprises performing an error correction code (ECC) operation on the cache line containing the cache error to correct the cache error and outputting the corrected cache line from the cache.

14. The method of claim 11 further comprising:

assigning a third value of the control value within the user programmable error action control register to implement automatic correction of the detected error and generates an exception.

15. The method of claim 11 further comprising:

setting the control value to the first value during a first portion of a time interval wherein a first portion of an application is executed with transparency of cache errors to the processor; and

setting the control value to the second value during a second portion of the time interval wherein a second portion of the application is executed with cache errors being visible to the processor.

16. The method of claim 11 further comprising:

providing a second control value in the user programmable error action control register, the second control value controlling enablement of the error detection of the cache control circuitry.

17. The method of claim 11 further comprising:

assigning a third value of the control value within the user programmable error action control register to implement an automatic invalidation of the cache line containing the cache error if the cache line is a clean cache line, and if the cache line is a dirty cache line an exception is generated and the cache line is left unaltered such that the cache line is not invalidated.

Assignments (19)