Array substrate and method of manufacturing the same
View Patent ↗An array substrate includes a base substrate, a gate line, a gate insulation layer, a data line, a thin-film transistor (“TFT”) and a pixel electrode. The gate line includes a gate covering line formed in a first direction on the base substrate and a gate main line protruded from the gate covering line. The gate insulation layer is formed on the base substrate to cover the gate line. The data line is formed on the gate insulation layer in a second direction crossing the first direction. The TFT is electrically connected to the gate line and the data line. The pixel electrode is electrically connected to the TFT. Therefore, a gate line is thicker than a gate covering line and a gate main line having a low resistance is further formed, so that a gate signal may be quickly transferred along the gate line without a signal delay.
1. An array substrate comprising:
a base substrate;
a gate line including a gate covering line formed in a first direction on the base substrate and a gate main line protruded from the gate covering line;
a gate insulation layer formed on the base substrate to cover the gate line;
a data line formed on the gate insulation layer in a second direction crossing the first direction;
a thin-film transistor electrically connected to the gate line and the data line; and
a pixel electrode electrically connected to the thin-film transistor,
wherein the base substrate includes a gate receiving groove formed thereon, the gate receiving groove receives the gate main line.
2. The array substrate of claim 1 , wherein an upper surface of the gate main line received in the gate receiving groove is substantially coplanar with an upper surface of the base substrate.
3. The array substrate of claim 1 , further comprising a gate buffer layer formed between the base substrate and the gate line, the gate buffer layer having a gate receiving groove that receives the gate main line.
4. The array substrate of claim 3 , wherein an upper surface of the gate main line received in the gate receiving groove is substantially coplanar with an upper surface of the gate buffer layer.
5. The array substrate of claim 1 , wherein a thickness of the gate main line is thicker than that of the gate covering line.
6. The array substrate of claim 1 , wherein the gate covering line comprises:
a gate covering portion formed along the first direction to cover the gate main line; and
a laser shorting portion protruded from the gate covering portion toward the pixel electrode to be overlapped by a portion of the pixel electrode.
7. The array substrate of claim 6 , wherein a gate electrode of the TFT is protruded from the gate covering portion toward the pixel electrode.
8. The array substrate of claim 7 , wherein a portion of the gate main line is formed below the gate electrode to be covered by the gate electrode.
9. The array substrate of claim 1 , wherein the data line comprises:
a data main line formed along the second direction; and
a data covering line formed along the second direction to cover the data main line.
10. The array substrate of claim 9 , wherein the data covering line is formed on the gate insulation layer, and the data main line is formed on the data covering line.
11. The array substrate of claim 10 , further comprising a data buffer layer formed on the gate insulation layer, the data buffer layer having a data receiving hole exposing at least a portion of the data covering line and receiving the data main line.
12. The array substrate of claim 9 , wherein the data main line is formed on the gate insulation layer, and the data covering line is formed on the data main line.
13. The array substrate of claim 12 , wherein the gate insulation layer has a data receiving groove formed through the gate insulation layer, which receives the data main line.
14. An array substrate comprising:
a base substrate;
a gate line formed on the base substrate;
a gate insulation layer formed on the base substrate to cover the gate line;
a data line formed on the gate insulation layer and crossing the gate line;
a thin-film transistor electrically connected to the gate line and the data line and having a gate electrode electrically connected to the gate line; and
a pixel electrode electrically connected to the thin-film transistor,
wherein the gate electrode of the thin-film transistor is thinner than a thinnest portion of the gate line.
15. The array substrate of claim 14 , wherein the gate line includes a gate covering line formed on the base substrate and a gate main line disposed under the gate covering line.
16. The array substrate of claim 15 , wherein the gate main line is thicker than the gate electrode of the thin-film transistor.
17. The array substrate of claim 16 , wherein the gate electrode of the thin-film transistor is protruded from the gate covering line toward the pixel electrode.
18. The array substrate of claim 14 , wherein the base substrate includes a gate receiving groove receiving the gate main line.
19. The array substrate of claim 15 , wherein the gate covering line has a thickness substantially same as the gate electrode.
20. The array substrate of claim 15 , wherein the gate covering line has a width greater than the gate main line.