THIN FILM TRANSISTOR SUBSTRATE, LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME
A thin film transistor (“TFT”) substrate includes first through third TFTs, first and second sub pixel electrodes, and a voltage down capacitor. A control terminal and an input terminal of the first and the second TFT are connected to an (N- 1 )-th gate line and a data line, respectively. The first sub pixel electrode is connected to an output terminal of the first TFT. The second sub pixel electrode is connected to an output terminal of the second TFT. A control terminal and an input terminal of the third TFT are connected to an N-th gate line and the first sub pixel electrode, respectively. The voltage down capacitor is connected to an output terminal of the third TFT. A maximum data voltage transferred from the data line to at least one of the first and second sub pixel electrodes has a range of approximately 14 volts to approximately 16 volts.
1 . A thin film transistor substrate comprising:
a first thin film transistor and a second thin film transistor, each transistor electrically connected to an (N- 1 )-th gate line (where N is a natural number) and a data line;
a first sub pixel electrode electrically connected to the first thin film transistor;
a second sub pixel electrode electrically connected to the second thin film transistor;
a third thin film transistor electrically connected to an N-th gate line and the first sub pixel electrode; and
a voltage down capacitor electrically connected to the third thin film transistor,
wherein a maximum data voltage transferred from the data line to at least one of the first sub pixel electrode and the second sub pixel electrode has a range of approximately 14 volts to approximately 16 volts.
2 . The thin film transistor substrate of claim 1 , wherein the voltage down capacitor decreases a voltage level charged to the first sub pixel electrode.
3 . The thin film transistor substrate of claim 1 , wherein
the first thin film transistor comprises:
a first source electrode which overlaps at least a first portion of the (N- 1 )-th gate line;
a first drain electrode disposed adjacent to the first source electrode and electrically connected to the first sub pixel electrode; and
a first semiconductor pattern disposed between the (N- 1 )-th gate line and at least one of the first source electrode and the first drain electrode,
the second thin film transistor comprises:
a second source electrode which overlaps at least a second portion of the (N- 1 )-th gate line;
a second drain electrode disposed adjacent to the second source electrode and electrically connected to the second sub pixel electrode; and
a second semiconductor pattern disposed between the (N- 1 )-th gate line and at least one of the second source electrode and the second drain electrode, and
the third thin film transistor comprises:
a third source electrode which overlaps at least a third portion of the (N- 1 )-th gate line;
a third drain electrode disposed adjacent to the third source electrode and electrically connected to the third sub pixel electrode; and
a third semiconductor pattern disposed between the (N- 1 )-th gate line and at lest one of the third source electrode and the third drain electrode.
4 . The thin film transistor substrate of claim 3 , further comprising:
an insulation substrate; and
a storage line disposed on the insulation substrate between the (N- 1 )-th gate line and the N-th gate line, wherein
the voltage down capacitor comprises a portion of the storage line, a portion of a gate insulation layer disposed on the storage line, a portion of a third semiconductor pattern disposed on the gate insulation layer and a portion of the third drain electrode.
5 . The thin film transistor substrate of claim 4 , wherein
the maximum data voltage comprises a first maximum voltage charged to the first sub pixel electrode, and
the first maximum voltage has a range of approximately 45 percent to approximately 95 percent of a second maximum voltage charged to the second sub pixel electrode.
6 . The thin film transistor substrate of claim 5 , wherein the voltage down capacitor decreases a voltage level charged to the first sub pixel electrode.
7 . The thin film transistor substrate of claim 6 , wherein an area of the second sub pixel electrode is greater than approximately 1.1 times an area of the first sub pixel electrode.
8 . The thin film transistor substrate of claim 6 , wherein an area of the first sub pixel electrode is greater than approximately 1.1 times an area of the second sub pixel electrode.
9 . The thin film transistor substrate of claim 1 , wherein a polarity of a data voltage supplied to at least one of the first sub pixel electrode and the second sub pixel electrode is reversed each consecutive frame.
10 . The thin film transistor substrate of claim 1 , wherein a shape of at least one of the first pixel electrode and the second sub pixel electrode comprises a chevron shape.
11 . A liquid crystal panel comprising:
a color filter substrate comprising a common electrode and a color filter disposed on the common electrode;
a thin film transistor substrate disposed opposite to the color filter substrate; and
a vertically aligned liquid crystal layer disposed between the color filter substrate and the thin film transistor substrate,
wherein the thin film transistor substrate comprises:
a first thin film transistor and a second thin film transistor, each transistors electrically connected to an (N- 1 )-th gate line (where N is a natural number) and a data line;
a first sub pixel electrode electrically connected to the first thin film transistor;
a second sub pixel electrode electrically connected to the second thin film transistor;
a third thin film transistor electrically connected to an N-th gate line and the first sub pixel electrode; and
a voltage down capacitor electrically connected to the third thin film transistor,
wherein a maximum data voltage transferred from the data line to at least one of the first sub pixel electrode and the second sub pixel electrode has a range of approximately 14 volts to approximately 16 volts.
12 . The liquid crystal panel of claim 11 , wherein
the maximum data voltage comprises a first maximum voltage charged to the first sub pixel electrode, and
the first maximum voltage has a range of approximately 45 percent to approximately 95 percent of a second maximum voltage charged to the second sub pixel electrode.
13 . The liquid crystal panel of claim 12 , wherein the voltage down capacitor decreases a voltage level charged to the first sub pixel electrode.
14 . The liquid crystal panel of claim 12 , wherein
the thin film transistor substrate further comprises a storage line which supplies a storage voltage to at least one of the first sub pixel electrode and the second sub pixel electrode,
the storage line overlaps at least a portion of the first sub pixel electrode and the second sub pixel electrode,
an insulation layer is disposed between the storage line and the at least a portion of the first sub pixel electrode and the second sub pixel electrode to form a first capacitor and a second capacitor,
the voltage down capacitor overlaps at least a portion of each of the storage line and a drain electrode of the third thin film transistor, and
an insulation layer is disposed between the voltage down capacitor and each of the storage line and the drain electrode of the third thin film transistor.
15 . The liquid crystal panel of claim 14 , wherein the common electrode comprises a slit which divides a pixel area into a plurality of domains.
16 . The liquid crystal panel of claim 15 , wherein at least one of the first sub pixel electrode and the second sub pixel electrode further comprises a cutting part.
17 . The liquid crystal panel of claim 16 , wherein the storage line overlaps at least a portion of the cutting part.
18 . The liquid crystal panel of claim 11 , wherein a polarity of a data voltage supplied to at least one of the first sub pixel electrode and the second sub pixel electrodes is reversed each consecutive frame.
19 . A method of manufacturing a thin film transistor substrate, the method comprising:
forming an insulation substrate;
forming a gate metallic layer on the insulation substrate;
etching gate lines, gate electrodes and a storage line from the gate metallic layer using a first mask;
forming a gate insulation layer, an amorphous silicon layer and an amorphous silicon layer implanted with impurities on the gate metallic layer;
forming a data metallic layer on the amorphous silicon layer implanted with impurities;
etching the data metallic layer using a second mask to form a first thin film transistor, a second thin film transistor and a third thin film transistor;
forming a protective layer on the data metallic layer using a third mask;
forming a first sub pixel electrode and a second sub pixel electrode using a fourth mask;
connecting the first thin film transistor and the second thin film transistor to an (N- 1 )-th gate line (where N is a natural number) and a data line;
connecting the first thin film transistor to the first sub pixel electrode;
connecting the second thin film transistor to the second sub pixel electrode;
connecting the third thin film transistor to an N-th gate line and the first sub pixel electrode; and
forming a voltage down capacitor by overlapping the storage line with a drain electrode of the third transistor;
wherein a maximum data voltage transmitted from the data line to at least one of the first sub pixel electrode and the second sub pixel electrode has a range of approximately 14 volts to approximately 16 volts.
20 . The method of claim 19 , wherein the voltage down capacitor decreases a voltage level charged to the first sub pixel electrode.