Thin film transistor substrate and display apparatus having the same
View Patent ↗A TFT substrate with reduced pixel defect rate is presented. The TFT substrate includes a pixel electrode, a negative line to apply a reverse voltage to the pixel electrode, and a recovery transistor including a drain electrode overlapping a part of the negative line with a insulating layer disposed between the negative line and the drain electrode. A contact hole is formed on the negative line and the drain electrode, and a bridge electrode connects the negative line and the drain electrode through the contact hole. The thin film transistor substrate and a display apparatus presented herein protect a data line assembly metal layer and decrease pixel defect. An improved reverse voltage efficiency is applied to a pixel electrode to protect a drain electrode.
1. A TFT substrate comprising:
a gate line coupled to a first transistor;
a negative line transmitting a reverse voltage;
a second transistor comprising a drain electrode overlapping a part of the negative line with an insulating layer disposed between the negative line and the drain electrode;
a contact hole formed on the negative line and the drain electrode; and
a bridge electrode connecting the negative line and the drain electrode through the contact hole.
2. The TFT substrate according to claim 1 , further comprising:
a data line insulated from the gate line;
a voltage supply line; and
a pixel electrode.
3. The TFT substrate according to claim 2 , wherein the voltage supply line is parallel to the data line, and the data line and the voltage supply line are alternately provided.
4. The TFT substrate according to claim 2 , wherein the voltage supply line is provided on the same layer as the data line.
5. The TFT substrate according to claim 2 , wherein the first transistor is coupled to the data line.
6. The TFT substrate according to claim 2 , further comprising a third transistor coupled to the first transistor, the voltage supply line and the pixel electrode.
7. The TFT substrate according to claim 6 , wherein the second transistor is coupled to a gate electrode of the third transistor.
8. The TFT substrate according to claim 2 , further comprising a light emitting layer provided on the pixel electrode.
9. The TFT substrate according to claim 1 , wherein the contact hole does not overlap a boundary area between the negative line and the drain electrode.
10. The TFT substrate according to claim 1 , wherein an area of a base of the contact hole disposed on the drain electrode is approximately 50 μm 2 -100 μm 2 .
11. The TFT substrate according to claim 1 , wherein an area of a base of the contact hole disposed on the negative line is approximately 40 μm 2 -70 μm 2 .
12. The TFT substrate according to claim 1 , wherein the contact hole has an approximately rectangular base, a short side of the rectangle is parallel to a width direction of the negative line, and a length of the short side is approximately one-third of the width of the negative line.
13. The TFT substrate according to claim 1 , wherein the bridge electrode comprises indium tin oxide, indium zinc oxide, amorphous indium tin oxide or amorphous indium zinc oxide.
14. The TFT substrate according to claim 1 , further comprising a recovery line to apply a recovery-on voltage to the second transistor.
15. The TFT substrate according to claim 1 , wherein the first transistor apply a data voltage.
16. The TFT substrate according to claim 1 , wherein the negative line is provided on the same layer as the gate line.