Semiconductor device having a trench type high-power MISFET
The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate.
1. A semiconductor device comprising:
(a) an active cell which causes a load current to flow therethrough;
(b) a sense cell which detects a magnitude of the load current flowing through the active cell; and
(c) an inactive cell which separates the active cell and the sense cell from each other,
wherein each of the active cell, the sense cell and the inactive cell includes:
(d1) a first semiconductor region of a first conduction type formed over a first surface of a semiconductor substrate corresponding to the first conduction type;
(d2) a second semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type, said second semiconductor region being formed over the first semiconductor region;
(d3) a trench which penetrates the second semiconductor region to reach the first semiconductor region and is formed so as not to reach the semiconductor substrate;
(d4) a first insulating film formed in parts of a bottom face of the trench and a side surface thereof;
(d5) a dummy gate electrode formed inside the trench via the first insulating film;
(d6) a second insulating film formed so as to cover an upper portion of the dummy gate electrode;
(d7) a gate electrode provided over the second insulating film and formed inside the trench;
(d8) a gate insulating film formed between the side surface of the trench and the gate electrode; and
(d9) a drain region comprising the semiconductor substrate corresponding to the first conduction type, and
wherein (d10) each of the active cell and the sense cell further has a source region formed in alignment with the trench and comprising a semiconductor region of the first conduction type formed over the second semiconductor region, whereas the inactive cell does not include the source region,
wherein the dummy gate electrode and the gate electrode are electrically coupled to each other,
wherein the trench with the dummy gate electrode and the gate electrode embedded therein is formed in plural form so as to be arranged in a first direction of the semiconductor substrate, and
wherein the respective trenches are formed so as to extend in a second direction orthogonal to the first direction,
wherein first trenches of the respective trenches which extend in the second direction through an active cell forming area formed with the active cell, a sense cell forming area formed with the sense cell and an inactive cell forming area formed with the inactive cell, exist,
wherein gate electrodes embedded in the first trenches extending in the second direction through the active cell forming area, the sense cell forming area and the inactive cell forming area function as a gate electrode of the active cell in the active cell forming area, function as a gate electrode of the sense cell in the sense cell forming area, and function as a gate electrode of the inactive cell in the inactive cell forming area, respectively, and
wherein the first trenches adjacent to one another are coupled by blocking trenches extending in the first direction.
2. The semiconductor device according to claim 1 , wherein the blocking trenches are formed in the inactive cell forming area and the sense cell forming area.
3. The semiconductor device according to claim 2 , wherein the blocking trenches are formed so as to differ in forming position for every said first trenches adjacent to each other.
4. The semiconductor device according to claim 2 , wherein the blocking trenches extend in alignment in the first direction so as to intersect with the first trenches extending in the second direction side by side in the first direction.
5. The semiconductor device according to claim 2 , wherein the blocking trenches have the same structure as the first trenches.
6. A semiconductor device comprising:
(a) an active cell which causes a load current to flow therethrough;
(b) a sense cell which detects a magnitude of the load current flowing through the active cell; and
(c) an inactive cell which separates the active cell and the sense cell from each other,
wherein each of the active cell, the sense cell and the inactive cell includes:
(d1) a first semiconductor region of a first conduction type formed over a first surface of a semiconductor substrate corresponding to the first conduction type;
(d2) a second semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type, said second semiconductor region being formed over the first semiconductor region;
(d3) a trench which penetrates the second semiconductor region to reach the first semiconductor region and is formed so as not to reach the semiconductor substrate;
(d4) a first insulating film formed in parts of a bottom face of the trench and a side surface thereof;
(d5) a dummy gate electrode formed inside the trench via the first insulating film;
(d6) a second insulating film formed so as to cover an upper portion of the dummy gate electrode;
(d7) a gate electrode provided over the second insulating film and formed inside the trench;
(d8) a gate insulating film formed between the side surface of the trench and the gate electrode; and
(d9) a drain region comprising the semiconductor substrate corresponding to the first conduction type, and
wherein (d10) each of the active cell and the sense cell further has a source region formed in alignment with the trench and comprising a semiconductor region of the first conduction type formed over the second semiconductor region, whereas the inactive cell does not include the source region,
wherein an active cell forming area formed with the active cell, a sense cell forming area formed with the sense cell, and an inactive cell forming area formed with the inactive cell exist in the semiconductor substrate,
wherein the sense cell forming area is formed in a region in which its periphery is surrounded by the active cell forming area, and
wherein the inactive cell forming area is formed between the sense cell forming area and the active cell forming area,
further including a source pad electrically coupled to the source region of the active cell, and a sense pad electrically coupled to the source region of the sense cell,
wherein electrical coupling between the source region of the active cell and the source pad is performed by a plug coupled to the source region of the active cell from an interlayer insulating film formed over the active cell, and a first wiring coupled to the plug and formed over the interlayer insulating film, and
wherein electrical coupling between the source region of the sense cell and the sense pad is performed by a plug coupled to the source region of the sense cell from the interlayer insulating film formed over the sense cell, and a second wiring coupled to the plug and formed in a layer above the first wiring.
7. The semiconductor device according to claim 6 ,
wherein an active cell forming area formed with the active cell, a sense cell forming area formed with the sense cell, and an inactive cell forming area formed with the inactive cell exist in the semiconductor substrate,
wherein the sense cell forming area has a region in which at least part thereof is not surrounded by the active cell forming area, and
wherein the inactive cell forming area is formed between the sense cell forming area and the active cell forming area.
8. The semiconductor device according to claim 7 , further including a source pad electrically coupled to the source region of the active cell, and a sense pad electrically coupled to the source region of the sense cell,
wherein electrical coupling between the source region of the active cell and the source pad is performed by a plug coupled to the source region of the active cell from an interlayer insulating film formed over the active cell, and a first wiring coupled to the plug and formed over the interlayer insulating film,
wherein electrical coupling between the source region of the sense cell and the sense pad is performed by a plug coupled to the source region of the sense cell from the interlayer insulating film formed over the sense cell, and a third wiring of the same layer as the first wiring coupled to the plug, and
wherein the third wiring is drawn from a region unsurrounded by the active cell forming area and coupled to the sense pad.
9. A semiconductor device comprising:
(a) an active cell which causes a load current to flow therethrough;
(b) a sense cell which detects a magnitude of the load current flowing through the active cell; and
(c) an inactive cell which separates the active cell and the sense cell from each other,
wherein each of the active cell, the sense cell and the inactive cell includes:
(d1) a first semiconductor region of a first conduction type formed over a first surface of a semiconductor substrate corresponding to the first conduction type;
(d2) a second semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type, said second semiconductor region being formed over the first semiconductor region;
(d3) a trench which penetrates the second semiconductor region to reach the first semiconductor region and is formed so as not to reach the semiconductor substrate;
(d4) a first insulating film formed in parts of a bottom face of the trench and a side surface thereof;
(d5) a dummy gate electrode formed inside the trench via the first insulating film;
(d6) a second insulating film formed so as to cover an upper portion of the dummy gate electrode;
(d7) a gate electrode provided over the second insulating film and formed inside the trench;
(d8) a gate insulating film formed between the side surface of the trench and the gate electrode; and
(d9) a drain region comprising the semiconductor substrate corresponding to the first conduction type, and
wherein (d10) each of the active cell and the sense cell further has a source region formed in alignment with the trench and comprising a semiconductor region of the first conduction type formed over the second semiconductor region, whereas the inactive cell does not include the source region,
wherein an electric field relaxation layer is formed between the active cell forming area formed with the active cell and the inactive cell forming area formed with the inactive cell.
10. The semiconductor device according to claim 9 , wherein the electric field relaxation layer is formed of a fourth semiconductor region of the second conduction type.