Semiconductor device and method of fabricating the same
View Patent ↗A semiconductor device and a method of fabricating the same include a gate electrode formed over the silicon substrate, the gate electrode including low-concentration conductive impurity regions, a high-concentration conductive impurity region formed between the low-concentration conductive impurity regions and a first silicide layer formed over the high-concentration conductive impurity region, and contact electrodes including a first contact electrode connected electrically to the gate electrode and a second contact electrode connected electrically to source/drain regions. The first contact electrode contacts the uppermost surface of the gate electrode and a sidewall of the gate electrode. The gate electrode can be easily connected to the contact electrode, the high-concentration region can be disposed only on the channel region, making it possible to maximize overall performance of the semiconductor device.
1. A device comprising:
a gate electrode formed over a semiconductor substrate;
spacers formed at sidewalls of the gate electrode and exposing a portion of the sidewalls of the gate electrode;
a source/drain region formed in the semiconductor substrate at lateral sides of the gate electrode; and
a contact electrode formed over the semiconductor substrate to contact the sidewalls and an uppermost surface of the gate electrode,
wherein the gate electrode comprises:
a high-concentration region into which a conductive impurity is implanted; and
a low-concentration region into which a conductive impurity having a lower-concentration than the high-concentration region is implanted, and
wherein the spacers comprise:
a first spacer formed directly contacting both the high-concentration region and the low-concentration region; and
a second spacer formed directly contacting both the first spacer and the high-concentration region.
2. The device of claim 1 , wherein the gate electrode further comprises a silicide layer formed over and contacting the high-concentration region.
3. The device of claim 1 , further comprising lightly doped drain (LDD) regions formed in the semiconductor substrate below and overlapping the spacers and the low-concentration region.
4. The device of claim 1 , wherein the high-concentration region is formed over a channel region of the semiconductor substrate and the low-concentration region is formed adjacent to and contacts a respective one of the spacers.
5. The device of claim 1 , wherein the spacers have a lower height than the gate electrode.
6. The device of claim 1 , wherein the low-concentration region is formed at bottom edge portions of the gate electrode, and the high-concentration region is formed between the low-concentration region and a silicide layer formed over and contacting the high-concentration region, wherein the high-concentration region is provided between the low-concentration region and the silicide layer to prevent the low-concentration region from directly contacting the silicide layer.
7. A device comprising:
a silicon substrate;
a gate electrode formed over the silicon substrate, the gate electrode including low-concentration conductive impurity regions formed spaced apart at bottom edge portions of the gate electrode, a high-concentration conductive impurity region formed between the low-concentration conductive impurity regions and a first silicide layer formed over the high-concentration conductive impurity region;
spacers formed at sidewalls of the gate electrode and exposing a portion of the sidewalls of the gate electrode;
source/drain regions formed in the silicon substrate adjacent lateral sides of the gate electrode;
a dielectric film formed over the silicon substrate including the gate electrode and the source/drain regions; and
contact electrodes formed penetrating through the dielectric film including a first contact electrode connected electrically to the gate electrode and a second contact electrode connected electrically to the source/drain regions, and
wherein the spacers comprise:
a first spacer formed directly contacting both the high-concentration conductive impurity region and at least one of the low-concentration conductive impurity regions; and
a second spacer formed directly contacting both the first spacer and the high-concentration impurity region.
8. The device of claim 7 , wherein the source/drain regions comprise:
a first source/drain region into which high-concentration conductive impurities are implanted and second source/drain region comprising a second silicide layer formed over the first source/drain region.
9. The device of claim 7 , wherein the high-concentration conductive impurity region corresponds to a channel region in the silicon substrate.
10. The device of claim 7 , further comprising:
a well formed in the silicon substrate;
shallow trench isolation films formed in the silicon substrate;
a gate dielectric film formed between the well and the gate electrode; and
lightly doped drain (LDD) regions formed in the well overlapping the spacers and the low-concentration conductive impurity regions and contacting the source/drain regions.
11. The device of claim 10 , wherein the high-concentration conductive impurity region corresponds to a region between the LDD regions.
12. The device of claim 7 , wherein the second spacer contacts:
an uppermost surface of the first spacer and a sidewall of the first spacer;
a portion of the sidewall of the first silicide layer and the high-concentration conductive impurity region.
13. The device of claim 7 , wherein the low-concentration conductive impurity regions are formed spaced apart at bottom edge portions of the gate electrode, and the high-concentration conductive impurity region is formed between the low-concentration conductive impurity regions and a silicide layer formed over and contacting the high-concentration conductive impurity region, wherein the high-concentration conductive impurity region is provided between the low-concentration conductive impurity regions and the silicide layer to prevent the low-concentration conductive impurity regions from directly contacting the silicide layer.
14. A method comprising:
forming a gate electrode over a silicon substrate, the gate electrode including first conductive impurity regions formed spaced apart at bottom edge portions of the gate electrode, a second conductive impurity region formed between the first conductive impurity regions and a first silicide layer formed over the second conductive impurity region; and then
forming spacers exposing a portion of sidewalls of the gate electrode, wherein forming the spacers comprises:
forming a first spacer directly contacting both the first conductive impurity regions and the second conductive impurity region; and then
forming a second spacer directly contacting both the first spacer and the second conductive impurity region; and then
forming source/drain regions in the silicon substrate adjacent lateral sides of the gate electrode; and then
forming a dielectric film over the silicon substrate including the gate electrode and the source/drain regions; and then
forming a first contact electrode in the dielectric film connected electrically to the gate electrode and a second contact electrode in the dielectric film connected electrically to the source/drain regions, wherein the first contact electrode contacts the uppermost surface of the gate electrode and a sidewall of the gate electrode.
15. The method of claim 14 , wherein the first gate electrode conductive impurity regions comprises low-concentration conductive impurity regions and the second conductive impurity region comprises a high-concentration conductive impurity region.
16. The method of claim 14 , further comprising, before forming the gate electrode, forming a well formed in the silicon substrate, wherein the gate electrode is formed over the well and the source/drain regions are formed in the well.
17. The method of claim 16 , further comprising, before forming the source/drain regions: forming lightly doped drain (LDD) regions in the well overlapping the spacers and the first conductive impurity regions.
18. The method of claim 14 , wherein the second conductive impurity region corresponds to a channel region in the silicon substrate.