Time-interleaved analog-to-digital-converter
View Patent ↗A method for operating a time-interleaved analog-to-digital converter for converting an analog input to a digital output using a time-interleaved analog-to-digital converter, wherein the time-interleaved analog-to-digital converter comprises an array of M sub ADCs (ADC 1 , ADC 2 , . . . , ADC M ), where M is an even integer, and each row of the array comprises one of the M sub ADCs. The method comprises the step of, for every sampling instant n, where n is an integer in a sequence of integers, converting the analog input by means of the sub ADC in row k(n) of the array, wherein 1≦k(n)≦M. A value between 1 and M is assigned to k(n) for the first sample instant, and k(n+1) is selected such that a) k(n+1)>M/2 if k(n)≦M/2, otherwise k(n+1)≦M/2; b) M/2−1≦|k(n+1)−k(n)|≦M/2+1; and c) k(n+1)=k(m+1) if and only if n−m is an integer multiple of M. A time interleaved analog-to-digital converter operating in accordance with the method is also disclosed.
1. A method for operating a time-interleaved analog-to-digital converter for converting an analog input to a digital output, wherein the time-interleaved analog-to-digital converter comprises an array of M sub ADCs (ADC 1 , ADC 2 , . . . , ADC M ), where M is an even integer, and each row of the array comprises one of the M sub ADCs, wherein
for every sampling instant n, where n is an integer in a sequence of integers, converting the analog input by means of the sub ADC in row k(n) of the array, wherein 1≦k(n)≦M, a value between 1 and M is assigned to k(n) for the first sampling instant, and k(n+1) is selected such that
a) k(n+1)>M/2 if k(n)≦M/2, otherwise k(n+1)≦M/2;
b) M/2−1≦|k(n+1)−k(n)|≦M/2+1; and
c) k(n+1)=k(m+1) if and only if n−m is an integer multiple of M.
2. The method according to claim 1 , wherein k(n+1) is chosen according to
if k(n)<M/2 and k(n) is odd, then k(n+1)=k(n)+M/2+1;
if k(n)=M/2 and k(n) is odd, then k(n+1)=M;
if k(n)≦M/2 and k(n) is even, then k(n+1)=k(n)+M/2−1;
if k(n)=M/2+1, then k(n+1)=1;
if k(n)>M/2+1 and k(n)−M/2 is odd, then k(n+1)=k(n)−M/2−1;
if k(n)=M and k(n)−M/2 is even, then k(n+1)=M/2; or
if M/2+1<k(n)<M and k(n)−M/2 is even, then k(n+1)=k(n)−M/2+1.
3. The method according to claim 1 , wherein M/2 is an odd number and k(n+1) is chosen according to
if k(n)=1 then k(n+1) is set to M/2+1;
if k(n)≦M/2, k(n)≠1, and k(n) is odd, then k(n+1) is set to k(n)+M/2−1;
if k(n)≦M/2 and k(n) is even, then k(n+1) is set to k(n)+M/2+1;
if k(n)=M then k(n+1) is set to M/2;
if M/2<k(n)<M and k(n) is odd, then k(n+1) is set to k(n)−M/2−1; or
if M/2<k(n)<M and k(n) is even, then k(n+1) is set to k(n)−M/2+1.
4. A computer program product comprising computer program code means for executing the method according to claim 1 , when said computer program code means are run by an electronic device having computer capabilities.
5. A computer readable medium having stored thereon a computer program product comprising computer program code means for executing the method according to claim 1 , when said computer program code means are run by an electronic device having computer capabilities.
6. A time-interleaved analog-to-digital converter comprising an array of M sub ADCs (ADC 1 , . . . , ADC M ), where M is an even integer, wherein each row of the array comprises one of the M sub ADCs (ADC 1 , . . . , ADC M ), wherein
a control unit arranged to, for every sampling instant n, where n is an integer in a sequence of integers, select the sub ADC in row k(n), 1≦k(n)≦M, of the array that is used for converting an analog input to a digital output, wherein the control unit is adapted to assign a value between 1 and M to k(n) for the first sampling instant and to, for a given value of k(n), select k(n+1) such that
a) k(n+1)>M/2 if k(n)≦M/2, otherwise k(n+1)≦M/2;
b) M/2−1≦|k(n+1)−k(n)|≦M/2+1; and
c) k(n+1)=k(m+1) if and only if n−m is an integer multiple of M.
7. The time-interleaved ADC according to claim 6 , wherein the control unit is arranged to select k(n+1) according to
if k(n)<M/2 and k(n) is odd, then k(n+1) is set to k(n)+M/2;
if k(n)=M/2 and k(n) is odd, then k(n+1) is set to M;
if k(n)≦M/2 and k(n) is even, then k(n+1) is set to k(n)+M/2−1;
if k(n)=M/2+1, then k(n+1) is set to 1;
if k(n)>M/2+1 and k(n)−M/2 is odd, then k(n+1) is set to k(n)−M/2−1;
if k(n)=M and k(n)−M/2 is even, then k(n+1) is set to M/2; or
if M/2+1<k(n)<M and k(n)−M/2 is even, then k(n+1) is set to k(n)−M/2+1.
8. The time-interleaved ADC according to claim 5 , wherein M/2 is an odd number and the control unit is arranged to select k(n+1) according to
if k(n)=1 then k(n+1) is set to M/2+1;
if k(n)≦M/2, k(n)≠1, and k(n) is odd, then k(n+1) is set to k(n)+M/2−1;
if k(n)≦M/2 and k(n) is even, then k(n+1) is set to k(n)+M/2+1;
if k(n)=M then k(n+1) is set to M/2;
if M/2<k(n)<M and k(n) is odd, then k(n+1) is set to k(n)−M/2−1; or
if M/2<k(n)<M and k(n) is even, then k(n+1) is set to k(n)−M/2+1.
9. The time-interleaved ADC according to claim 7 , wherein the control unit comprises a multi-phase clock unit arranged to generate an individual clock signal at each of a plurality of clock terminals (C 1 , . . . , C M ) of the multi-phase clock unit, and wherein each of said plurality of clock terminals (C 1 , . . . , C M ) are connected to one of the sub ADCs (ADC 1 , . . . , ADC M ).
10. The time-interleaved ADC according to claim 9 , wherein the multi-phase clock unit includes a delay-locked loop.
11. The time-interleaved ADC according to claim 9 , wherein the multi-phase clock generator includes a plurality of delay elements (D 1 , . . . , D M ) connected in a ring.
12. An integrated circuit comprising the time-interleaved ADC according to claim 6 .
13. An electronic apparatus comprising the time-interleaved ADC according to claim 6 .
14. The electronic apparatus according to claim 13 , wherein the electronic apparatus is a monitor, a projector, a television set, or a radio transceiver.