IP Library Granted Patent US 7,830,291
Granted Patent B2
US 7,830,291 · App. 12/279,437 · Granted Nov 9, 2010

Flexible analog-to-digital converter

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Quick Facts
Patent No.
US 7,830,291
App. No.
12/279,437
Granted
Nov 9, 2010
Kind
B2
Abstract

An analog-to-digital converter ( 1 ). The analog to digital converter ( 1 ) comprises a first range-control unit ( 100 ) adapted to generate a first range-control value for controlling a size of an input range of the analog-to-digital converter ( 1 ). The analog to digital converter further comprises a second range-control unit ( 200 ) adapted to generate a second range-control value for controlling a midpoint of the input range. Further, the analog-to-digital converter ( 1 ) comprises a reference-level unit ( 300 ) operatively connected to the first range-control unit ( 100 ) and the second range-control unit ( 200 ). The reference-level unit ( 300 ) is arranged to generate a plurality of reference levels at least based on the first and the second range-control value. The analog-to-digital converter further comprises a comparison unit ( 400 ) operatively connected to the second range-control unit ( 200 ) and the reference-level unit ( 300 ). The comparison unit ( 400 ) is arranged to perform at least one comparison between a difference between an analog input value of the analog-to-digital converter ( 1 ) and the second range-control value and individual reference levels of the plurality of reference levels. The comparison unit ( 400 ) is further arranged to generate a digital output value of the analog-to-digital converter ( 1 ) based on the at least one comparison.

Claims (25)

1. An analog-to-digital converter, comprising:

a first range-control unit adapted to generate a first range-control value for controlling a size of an input range of the analog-to-digital converter;

a second range-control unit adapted to generate a second range-control value for controlling an average value of a plurality of reference levels;

a reference-level unit operatively connected to the first range-control unit and the second range-control unit, wherein the reference-level unit is arranged to generate the plurality of reference levels at least based on the first and the second range-control value; and

a comparison unit operatively connected to the second range-control unit and the reference-level unit, wherein the comparison unit is arranged to perform at least one comparison between a difference between an analog input value of the analog-to-digital converter and the second range-control value and individual reference levels of the plurality of reference levels, and to generate a digital output value of the analog-to-digital converter based on the at least one comparison.

2. The analog-to-digital converter according to claim 1 , wherein the first range-control value controls a difference between a largest reference level and a smallest reference level of the plurality of reference levels.

3. The analog-to-digital converter according to claim 1 , wherein the average value of the plurality of reference levels is proportional to the second range-control value.

4. The analog-to-digital converter according to claim 1 , wherein the first range-control unit is digitally controllable via a first control interface and/or the second range-control unit is digitally controllable via a second control interface of the analog-to-digital converter.

5. The analog-to-digital converter according to claim 4 , wherein the first range-control unit includes a first MOS transistor, a digital-to-analog converter operatively connected to the first MOS transistor, and a first resistor string, and wherein the first range-control unit is arranged to generate the first range-control value on the gate terminal of the first MOS transistor, the digital-to-analog converter is arranged to control a drain current of the first MOS transistor, the first MOS transistor is arranged to inject said drain current into the first resistor string, and the first resistor string is arranged to generate at least one reference value for the second range-control unit.

6. The analog-to-digital converter according to claim 5 , wherein the second range-control unit includes a multiplexer unit arranged to select one of the at least one reference value generated by the first resistor string, and wherein the second range-control unit is further adapted to output the selected one of the at least one reference value or a value derived therefrom.

7. The analog-to-digital converter according to claim 1 , wherein the reference-level unit includes a second resistor string arranged to generate the plurality of reference levels at least based on a reference current injected into the second resistor string.

8. The analog-to-digital converter according to claim 7 , wherein the reference-level unit further includes a second MOS transistor arranged to receive the first range-control value at the gate terminal and to generate the reference current based on the first range-control value.

9. The analog-to-digital converter according to claim 7 , wherein the reference-level unit further includes an operational amplifier, OP, or operational transconductance amplifier, OTA, arranged to receive the second range-control value at a first input terminal of the OP or OTA and to supply a control voltage to the gate terminal of a third MOS transistor connected to the second resistor string, and wherein a second input terminal of the OP or OTA is connected to an internal node of the second resistor string.

10. An integrated circuit comprising an analog-to-digital converter according to claim 1 .

11. An electronic apparatus comprising an analog-to-digital converter according to claim 1 .

12. The electronic apparatus according to claim 11 , wherein the electronic apparatus is a monitor, a projector, a television set, or a radio transceiver.

13. The analog-to-digital converter according to claim 1 , wherein the second range-control value for controlling the average value of the plurality of reference levels is digitally controllable via a control interface of the analog-to-digital converter.

14. The analog-to-digital converter according to claim 13 , wherein the control interface is a first control interface, and wherein the first range-control value for controlling the size of the input range of the analog-to-digital converter is digitally controllable via a second control interface of the analog-to-digital converter.

15. An analog-to-digital converter, comprising:

a first range-control unit adapted to generate a first range-control value for controlling a size of an input range of the analog-to-digital converter;

a second range-control unit adapted to generate a second range-control value for controlling a midpoint of the input range;

a reference-level unit operatively connected to the first range-control unit and the second range-control unit, wherein the reference-level unit is arranged to generate a plurality of reference levels at least based on the first and the second range-control value; and

a comparison unit operatively connected to the second range-control unit and the reference-level unit, the comparison unit including at least one multiplexer unit arranged to select one of the plurality of reference levels and to forward the selected one of the plurality of reference levels to an output terminal of the at least one multiplexer unit, wherein the comparison unit is arranged to perform at least one comparison between a difference between an analog input value of the analog-to-digital converter and the second range-control value and individual reference levels of the plurality of reference levels, and to generate a digital output value of the analog-to-digital converter based on the at least one comparison.

16. The analog-to-digital converter according to claim 15 , wherein the at least one multiplexer unit in the comparison unit includes a plurality of MOS transistors arranged to forward one of the plurality of reference levels to the output of the multiplexer unit when set in a conducting state.

17. The analog-to-digital converter according to claim 16 , wherein each of the plurality of MOS transistors is operatively connected to a switch-control unit, and wherein each switch-control unit is adapted to set the MOS transistor operatively connected to it in the conducting state by connecting a charged capacitor to said MOS transistor.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2024
From: CSR TECHNOLOGY INC.
To: QUALCOMM INCORPORATED
Reel/Frame 069221/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2015
From: ZORAN CORPORATION
To: CSR TECHNOLOGY INC.
Reel/Frame 036642/0395 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: ZORAN CORPORATION
To: CSR TECHNOLOGY INC.
Reel/Frame 027550/0695 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2010
From: THE ESTATE OF SICON SEMICONDUCTOR AB C/O THE TRUSTEE ADVOKAT RUNE BRANNSTROM, ADVOKATFIRMAN GLIMSTEDT
To: ZORAN SWEDEN AB
Reel/Frame 023746/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2010
From: ZORAN SWEDEN AB
To: ZORAN CORPORATION
Reel/Frame 023746/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2008
From: WIKNER, JACOB
To: SICON SEMICONDUCTOR AB
Reel/Frame 021390/0800 →