Circuit for switching a voltage-controlled transistor
View Patent ↗A circuit including a voltage-controlled transistor to be switched. A first transistor is switched on, mediated by a control signal, and a first current flows through a series circuit and starts to subject a control input of the voltage-controlled transistor to charge reversal. The first current brings about a first potential shift at a connecting node. A second transistor is switched on by this first potential shift and a second current therefore flows through the switching path of the second transistor into the control input of the first transistor, which amplifies the first current. The increasing charge reversal of the control input of the voltage-controlled transistor brings about a second potential shift at the connecting node, the second transistor is switched off by this second potential shift, and the first transistor remains switched on, however, and holds the voltage-controlled transistor in its new switching state.
1. A circuit comprising a voltage-controlled transistor (T 4 ), comprising:
a first (+) and a second (−) supply potential (+,−);
a first (T 1 ) and a second transistor (T 2 ); and
an impedance (R 4 );
wherein a series circuit (R 4 , T 1 ) formed by a switching path of the first transistor (T 1 ) and the impedance (R 4 ) is coupled between the first supply potential (+) and a control input of the voltage-controlled transistor (T 4 ), wherein the impedance (R 4 ) is connected in a manner facing the first supply potential (+);
wherein the first supply potential (+) is coupled to a control input of the first transistor (T 1 ) via a switching path of the second transistor (T 2 );
wherein a control input of the second transistor (T 2 ) is coupled to a connecting node (V 1 ) between the impedance (R 4 ) and the switching path of the first transistor (T 1 ) in such a way that a potential change at the connecting node (V 1 ) switches the second transistor (T 2 );
wherein the circuit is configured in such a way that:
as a result of the first transistor (T 1 ) being switched on in a manner mediated by means of a control signal, a first current flows through the series circuit (R 4 , T 1 ) and starts to subject the control input of the voltage-controlled transistor (T 4 ) to charge reversal in a first sense,
the first current through the series circuit (R 4 , T 1 ) brings about a first potential shift at the connecting node (V 1 ),
the second transistor (T 2 ) is switched on by this first potential shift and a second current therefore flows through the switching path of the second transistor (T 2 ) into the control input of the first transistor (T 1 ), which amplifies the first current,
the increasing charge reversal of the control input of the voltage-controlled transistor (T 4 ) brings about a second potential shift at the connecting node (V 1 ),
the second transistor (T 2 ) is switched off by this second potential shift, and
the first transistor (T 1 ) remains switched on and holds the voltage-controlled transistor (T 4 ) in its new switching state; and
wherein the circuit further comprises a first capacitor (C 1 ) coupled between the connecting node (V 1 ) and the control input of the second transistor (T 2 ), the first capacitor being subjected to charge reversal by the first potential shift via a resistor (R 3 ) in series with the first capacitor (C 1 ) in such a way that it supports a switching off of the second transistor (T 2 ) by the second potential shift.
2. The circuit as claimed in claim 1 , in which the resistor (R 3 ) connected in series with the first capacitor (C 1 ) is configured in such a way that the charging time of the first capacitor (C 1 ) is shorter than the minimum duration for which the voltage-controlled transistor (T 4 ) stays in its new switching state.
3. The circuit as claimed in claim 1 , wherein the first transistor (T 1 ) is switched on via an open collector output of an operational amplifier (OP) and a pull-up resistor (R 1 ).
4. The circuit as claimed in claim 1 , comprising a third transistor (T 3 ), the control input of which is capacitively coupled to the control input of the voltage-controlled transistor (T 4 ) and the switching path of which is coupled in series between the first supply potential (+) and the control input of the second transistor (T 2 ), such that in the case of a potential shift in the direction of the second supply potential (−) at the control input of the voltage-controlled transistor (T 4 ), the third transistor (T 3 ) is switched on via its control input and a switching on of the second transistor (T 2 ) is prevented.
5. The circuit as claimed in claim 4 ,
wherein the first transistor (T 1 ) is switched on via an open collector output of an operational amplifier (OP) and a pull-up resistor (R 1 ); and
wherein the first capacitor (C 1 ) is coupled in a manner facing the control input of the second transistor (T 2 ), and the resistor (R 3 ) in series with the first capacitor (C 1 ) is coupled in the manner facing the connecting node (V 1 ) between the impedance (R 4 ) and the switching path of the first transistor (T 1 ), and wherein the switching path of the third transistor (T 3 ) is coupled between the first supply potential (+) and a node (V 5 ) between the first capacitor (C 1 ) and the resistor (R 3 ).
6. The circuit as claimed in claim 4 , wherein the control input of the third transistor (T 3 ) is coupled to the control input of the voltage-controlled transistor (T 4 ) via a second capacitor (C 2 ), and wherein a resistor (R 6 ) is coupled in parallel with the second capacitor (C 2 ) in order to increase the interference immunity.
7. The circuit as claimed in claim 6 , wherein a first diode (D 3 ) for discharging the second capacitor (C 2 ) is coupled between the control input of the third transistor (T 3 ) and the first supply potential (+).
8. The circuit as claimed in claim 1 , wherein a second diode (D 2 ) for discharging the first capacitor (C 1 ) is coupled between the control input of the second transistor (T 2 ) and the first supply potential (+).
9. The circuit as claimed in claim 1 , wherein a resistor (R 2 ) is coupled between the first supply potential and the control input of the second transistor (T 2 ).
10. The circuit as claimed in claim 3 , comprising a fourth transistor (T 5 ), the switching path of which is coupled between the control input of the voltage-controlled transistor (T 4 ) and the second supply potential (−), wherein the control input of the fourth transistor (T 5 ) is coupled to the open collector output of the operational amplifier (OP) in such a way that the open collector output switches on the fourth transistor (T 5 ) in order to subject the control input of the voltage-controlled transistor (T 4 ) to charge reversal in the remaining second sense via the switching path of the fourth transistor (T 5 ).
11. The circuit as claimed in claim 1 , comprising a third diode (D 1 ), wherein the circuit is designed to couple the third diode (D 1 ) between the control input of the voltage-controlled transistor (T 4 ) and the second supply potential via a switching path in order to subject said control input to charge reversal in the remaining second sense.
12. The circuit as claimed in claim 10 comprising a third transistor (T 3 ), the control input of which is capacitively coupled to the control input of the voltage-controlled transistor (T 4 ) and the switching path of which is coupled in series between the first supply potential (+) and the control input of the second transistor (T 2 ), such that in the case of a potential shift in the direction of the second supply potential (−) at the control input of the voltage-controlled transistor (T 4 ), the third transistor (T 3 ) is switched on via its control input and a switching on of the second transistor (T 2 ) is prevented; and
wherein at least one transistor from the group of the first (T 1 ), the second (T 2 ), the third (T 3 ) and the fourth transistor (T 5 ) is a bipolar transistor.