Window comparator with accurate levels for use in DC-DC converters
View Patent ↗The present invention relates to a improved feedback circuit for generating a quantized control signal representing the relation of a signal to be controlled relative to predetermined limits of at least one error signal window, the circuit comprising signal detecting means, a detected signal connected to error amplifying means for amplifying the error between the detected signal and a first reference signal, the output error signal of the error amplifying means connected to at least a first comparator means and second comparator means each configured to compare the error signal with one of the upper limit and lower limit of the at least one error signal window. The invention provides a circuit and method by which only one accurate comparator is needed and for the error windows only simple, inaccurate comparators can be used. Thus, accuracy of the distance between the defined error window levels is much more fixed because it is primary determined by mismatch of resistors and not by the offset of the used comparators. Further, the capacitive load on the feedback node is smaller, which leads to a better response time. Furthermore, the current consumption is considerably less. Moreover, the circuit will be smaller. Finally, yet importantly, the overall offset of the output voltage is comparable to the offset in the standard solution.
1. A feedback circuit configured to generate signals representing the relation of a voltage to be controlled relative to predetermined limits of at least one error signal window, the circuit comprising:
a voltage divider configured to divide an input voltage by a predetermined ratio;
an error amplifier coupled to the voltage divider and operative to detect and amplify an error between the divided input voltage and a positive reference voltage, and further operative to output an amplified error signal comprising the positive reference voltage offset by the amplified error;
at least one window comparator comprising a first comparator configured to compare the amplified error signal with an upper limit and a second comparator configured to compare the amplified error signal with a lower limit of the at least one error signal window.
2. The circuit according to claim 1 , further comprising an error window reference circuit configured to generate a plurality of error window reference voltages that are configured to provide the upper limit and the lower limit of the at least one error signal window.
3. The circuit according to claim 2 , wherein the error window reference circuit comprises a resistive divider coupled to a second reference voltage, the resistive divider being configured to provide as outputs the upper limit and the lower limit of the at least one error signal window.
4. The circuit according to claim 1 , wherein each of the first and second comparators corresponds to one of the limits of the at least one error signal window and is configured to provide as output a digital control signal indicating the relation of the amplified error signal to the respective limit.
5. The circuit according to claim 1 , wherein the error amplifier comprises an operational amplifier.
6. The circuit according to claim 1 , wherein the voltage divider is coupled to the output of a power supply circuit and the generated signals are coupled to an input to a control circuit of the power supply circuit, wherein the control circuit is configured to regulate the power supply circuit.
7. The circuit according to claim 6 , wherein the power supply circuit is a DC-DC-converter.
8. A method of windowing an input voltage, comprising:
dividing an input voltage by a predetermined ratio;
generating an error signal by subtracting a positive reference voltage from the divided input voltage;
amplifying the error signal;
adding the amplified error signal to the positive reference voltage as an offset;
comparing the sum of the amplified error signal and the positive reference voltage with upper and lower limits of at least one error window; and
outputting the results of the comparison as a quantized control signal.
9. The method according to claim 8 , wherein the method is performed in an electronic circuit to generate a digital feedback signal from an output voltage of the electronic circuit for control of the output voltage.
10. A feedback circuit configured to generate signals representing the relation of a voltage to be controlled relative to predetermined limits of at least one error signal window, the feedback circuit comprising:
a voltage divider configured to an input voltage by a predetermined ratio;
an error amplifier coupled to the voltage divider and configured to generate an amplified error signal by amplifying a difference between the divided input voltage and a first positive reference voltage, the amplified error signal comprising the sum of the first positive reference voltage and the amplified voltage difference; and
at least one window comparator, the at least one window comparator comprising a first comparator and a second comparator coupled to the error amplifier, each comparator configured to compare the amplified error signal with one of the upper limit and the lower limit of the at least one error signal window.
11. The circuit of claim 10 , wherein the first and second comparators are configured to generate a plurality of error window reference signals that are configured to provide the upper limit and the lower limit of the at least one error signal window.
12. The circuit of claim 11 , further comprising a resistive divider coupled to a second reference voltage and the first and second comparators, the resistive divider configured to provide as outputs the upper limit and the lower limit of the at least one error signal window.
13. The circuit of claim 10 , wherein each of the first and second comparators corresponds to one of the limits of the at least one error signal window and is configured to provide as output a digital control signal indicating the relation of the amplified error signal to the respective limit.
14. The circuit of claim 10 , wherein the error amplifier comprises an operational amplifier configured to multiply the difference between the input voltage and the first positive reference voltage by a predetermined factor.
15. The circuit of claim 10 , wherein the feedback circuit is coupled to an output of a power supply circuit and the generated signals are provided as an input to a control circuit of the power supply circuit, the control circuit configured to regulate the power supply circuit.
16. The circuit according to claim 15 , wherein the power supply circuit comprises a DC-DC-converter.