INTERPOLATION FUNCTION GENERATION CIRCUIT
An interpolation function generation circuit is formed by cascade connecting a first FIR filter ( 10 ) having a numerical value string composed of a ratio “−α, α, β, β, α, −α” (α is an emphasis coefficient and β is a fixed value) as a filter coefficient and a second FIR filter ( 20 ) having a numerical value string composed of a ratio “1, 3, 5, . . . , m−1, m−1, . . . , 5, 3, 1” when the tap length is an odd number and “1, 3, 5, . . . , n−2, n−1, n−2, . . . , 5, 3, 1” if the tap length is an odd number (m and n are multiples of the oversampling). With only the two FIR filter ( 10, 20 ), it is possible to easily realize an interpolation function having a variable emphasis.
1 . An interpolation function generation circuit, comprising:
a first FIR filter having a numerical value string composed of a ratio “−α, α, β, β, α, −α” (α and β are arbitrary coefficients with a value of 0 or greater) as a filter coefficient, and
a second FIR filter having a numerical value string composed of a ratio “1, 3, 5, . . . , m−1, m−1, . . . , 5, 3, 1” (m is an arbitrary even number greater than or equal to 2) or a numerical value string composed of a ratio “1, 3, 5, . . . , n−2, n−1, n−2, . . . , 5, 3, 1” (n is an arbitrary odd number greater than or equal to 3) as a filter coefficient,
the second FIR filter being cascade connected with the first FIR filter at a latter stage of the first FIR filter.
2 . The interpolation function generation circuit according to claim 1 ,
the first FIR filter has an emphasis arithmetic section which, with respect to a filter coefficient of a numerical value string composed of a ratio “−1, 1, β, β, 1, −1”, conducts an emphasis arithmetic operation on the basis of an emphasis coefficient α inputted, deriving a relation “−α, α, β, β, α, −α”.
3 . The interpolation function generation circuit according to claim 2 ,
the emphasis coefficient α is variable in the first FIR filter.
4 . The interpolation function generation circuit according to claim 1 ,
the second FIR filter has an oversampling circuit at its input stage, the oversampling circuit conducting oversampling of m-fold or n-fold with respect to input data.
5 . The interpolation function generation circuit according to claim 1 ,
the second FIR filter has an oversampling smoothing circuit in which an operation clock frequency is set to m times or n times an operation clock frequency of the first FIR filter.