IP Library Granted Patent US 8,012,835
Granted Patent B2
US 8,012,835 · App. 12/283,639 · Granted Sep 6, 2011

Method of high voltage operation of field effect transistor

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Quick Facts
Patent No.
US 8,012,835
App. No.
12/283,639
Granted
Sep 6, 2011
Kind
B2
Abstract

A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

Claims (21)

1. A method of high voltage operation of a field effect transistor, comprising:

providing a field effect transistor that includes a substrate, a source region and a drain region spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region;

supplying at least one of a signal electric potential and a signal current to the source region of the field effect transistor; and

supplying to the gate region of the field effect transistor a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential.

2. A method according to claim 1 ; wherein the providing step comprises providing a capacitive element connected between the drain region and the gate region.

3. A method according to claim 1 ; wherein in the providing step, the substrate comprises a semiconductor substrate.

4. A method according to claim 1 ; wherein in the providing step, the substrate comprises a semiconductor thin film disposed on a surface of a supporting substrate and insulated from the supporting substrate.

5. A method of high voltage operation of a field effect transistor, comprising:

providing a field effect transistor that includes a substrate, a source region and a drain region spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region;

providing a bias circuit comprised of two serial-connected resistors having a first end connected to the drain region and a second end;

supplying at least one of a signal electric potential and a signal current to the source region of the field effect transistor;

supplying to the gate region of the field effect transistor a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential;

supplying to the second end of the two serial-connected resistors an electric potential of a high voltage power supply; and

supplying a bias electric potential from a node between the two serial-connected resistors to the gate region.

6. A method of high voltage operation of a field effect transistor, comprising:

providing a field effect transistor that includes a substrate, a source region and a drain region spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region;

providing a bias circuit comprised of a rectifying device having one side connected in series to the drain region, and a resistor connected to the rectifying device;

supplying at least one of a signal electric potential and a signal current to the source region of the field effect transistor;

supplying to the gate region of the field effect transistor a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential;

supplying a first constant electric potential to a side of the resistor; and

supplying a bias electric potential from a node between the rectifying device and the resistor to the gate region.

Assignments (2)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2016
From: SEIKO INSTRUMENTS INC.
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 038058/0892 →