Analog-to-digital converter
View Patent ↗A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.
1. An ADC pipeline unit for converting input analog values to N-bit digital representations, the ADC pipeline unit implemented as a single integrated circuit and comprising:
M lookahead pipeline stages, each lookahead pipeline stage generating 1 raw bit for a total of M raw bits, with M>N, the stages including open-loop residue amplifiers, the M lookahead pipeline stages comprising an input sample-and-hold stage for receiving the input analog value, the input sample-and-hold stage including:
an input node;
a main capacitor coupled between a first node and ground;
a buffer having an input;
a first switch(es) coupled between the input node and the main capacitor, and between the input node and the input to the buffer; and
a second switch coupled between the first node and the input to the buffer;
the first switch(es) closed and the second switch open during a sample phase and the first switch(es) open and the second switch closed during a hold phase; and
a calibration unit coupled to the lookahead pipeline stages to compensate for non-linearity in the open-loop residue amplifiers.
2. The ADC pipeline unit of claim 1 wherein the M lookahead pipeline stages further comprise:
a first lookahead pipeline half-stage coupled to the input sample-and-hold, for producing a first raw bit; and
M-1 lookahead pipeline stages coupled in series to the first lookahead pipeline half-stage, each lookahead pipeline stage producing an additional raw bit;
wherein each of the half-stage and the first M-2 stages includes an open-loop residue amplifier.
3. The ADC pipeline unit of claim 2 wherein:
the first lookahead pipeline half-stage includes a single comparator for determining the first raw bit; and
each of the M-1 lookahead pipeline stages includes two comparators, one comparator for determining the raw bit for the stage assuming that the raw bit from a previous stage was 0 and another comparator for determining the raw bit for the stage assuming that the raw bit from the previous stage was 1.
4. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages can operate at a conversion rate of 1.25 GS/s or higher at an effective resolution of at least 5 bits per sample.
5. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages can operate at a quantization energy of 0.3 pJ/conv-step or less.
6. The ADC pipeline unit of claim 1 wherein N≧8.
7. The ADC pipeline unit of claim 1 wherein N≧5.
8. An ADC pipeline unit for converting input analog values to N-bit digital representations, the ADC pipeline unit implemented as a single integrated circuit and comprising:
M lookahead pipeline stages, each lookahead pipeline stage generating 1 raw bit for a total of M raw bits, with M>N, the stages including open-loop residue amplifiers;
a calibration unit coupled to the lookahead pipeline stages to compensate for non-linearity in the open-loop residue amplifiers; and
a circuit for adjusting a duty cycle of a clock signal, wherein the lookahead pipeline stages include comparators that generate the 1 raw bit for the stages, the comparators clocked by the clock signal, the duty cycle of the clock signal determining a settling period and a decision period for the comparator.
9. The ADC pipeline unit of claim 8 wherein the circuit for adjusting a duty cycle of a clock signal comprises:
an input node for receiving a clock signal;
a series of delay circuits, a beginning of the series coupled to the input node, the series creating a plurality of delayed clock signals;
a multiplexer coupled to the delay circuits to receive the plurality of delayed clock signals as inputs, the multiplexer selecting one of the delayed clock signals as an output; and
a logic circuit coupled to the input node and to the output of the multiplexer, for combining the clock signal with the delayed clocked signal to produce a clock signal of adjustable duty cycle.
10. The ADC pipeline unit of claim 8 wherein the M lookahead pipeline stages comprise:
an input sample-and-hold stage for receiving the input analog value;
a first lookahead pipeline half-stage coupled to the input sample-and-hold, for producing a first raw bit; and
M-1 lookahead pipeline stages coupled in series to the first lookahead pipeline half-stage, each lookahead pipeline stage producing an additional raw bit;
wherein each of the half-stage and the first M-2 stages includes an open-loop residue amplifier.
11. The ADC pipeline unit of claim 10 wherein:
the first lookahead pipeline half-stage includes a single comparator for determining the first raw bit; and
each of the M-1 lookahead pipeline stages includes two comparators, one comparator for determining the raw bit for the stage assuming that the raw bit from a previous stage was 0 and another comparator for determining the raw bit for the stage assuming that the raw bit from the previous stage was 1.
12. The ADC pipeline unit of claim 8 wherein the lookahead pipeline stages can operate at a conversion rate of 1.25 GS/s or higher at an effective resolution of at least 5 bits per sample.
13. The ADC pipeline unit of claim 8 wherein the lookahead pipeline stages can operate at a quantization energy of 0.3 pJ/conv-step or less.
14. The ADC pipeline unit of claim 8 wherein N≧8.
15. The ADC pipeline unit of claim 8 wherein N≧5.