Low-distortion voltage variable capacitor assemblies

1. An apparatus that receives a signal voltage, the apparatus comprising:

a capacitive network that includes a first half cell connected in parallel with a second half cell,

wherein the first half cell comprises a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which a first VVC of said two or more VVCs with a same bias voltage orientation as the signal voltage associated with said apparatus assumes one capacitance and a second VVC of said two or more VVCs with an opposite bias voltage orientation as the signal voltage assumes another capacitance, and

wherein the second half cell comprises a circuit with two or more VVCs configured in anti-series in which a third VVC of said two or more VVCs with the same bias voltage orientation as the signal voltage associated with said apparatus assumes the same values as said anti-oriented VVCs in said first half cell and a fourth VVC with the opposite bias voltage orientation as the signal voltage assumes the same values as said like-oriented VVCs in said first half cell;

a first Direct Current (DC) feed connected between the first VVC and the second VVC; and

a second DC feed connected between the third VVC and the fourth VVC,

wherein said VVCs are voltage tunable dielectric capacitors,

wherein values for the voltage tunable dielectric capacitors are selected based on reducing an error function over a desired range of bias and signal voltages as a function of a capacitance-voltage curve that numerically models the voltage tunable dielectric capacitors, and

wherein the error function is based on a change in a net capacitance of the capacitive network.

2. The apparatus of claim 1 , further comprising resistors or inductors connected to each node in said first and said second half-cells so that each node can be connected to either ground or a bias voltage source.

3. An apparatus that receives a signal voltage, the apparatus comprising:

a capacitive network that includes a first half cell connected in parallel with a second half cell,

wherein the first half cell comprises a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which a first VVC of said two or more VVCs with a same bias voltage orientation as the signal voltage associated with said apparatus assumes one capacitance and a second VVC of said two or more VVCs with an opposite bias voltage orientation as the signal voltage assumes another capacitance, and

wherein the second half cell comprises a circuit with two or more VVCs configured in anti-series in which a third VVC of said two or more VVCs with the same bias voltage orientation as the signal voltage associated with said apparatus assumes the same values as said anti-oriented VVCs in said first half cell and a fourth VVC with the opposite bias voltage orientation as the signal voltage assumes the same values as said like-oriented VVCs in said first half cell;

a first Direct Current (DC) feed connected between the first VVC and the second VVC; and

a second DC feed connected between the third VVC and the fourth VVC,

wherein said apparatus is adapted to allow for a desired total capacitance minimally dependent of said signal voltage by setting a required bias voltage,

wherein values for the VVCs are selected based on reducing an error function over a desired range of the received signal voltage as a function of a capacitance-voltage curve associated with the VVCs, and

wherein the error function is based on a change in a net capacitance of the capacitive network.

4. The apparatus of claim 3 , further comprising resistors or inductors connected to each node in said cell so that each node can be connected to either ground or a bias voltage source.

5. The apparatus of claim 3 , wherein said two or more voltage variable capacitors in said first-half and said second-half cell are configured to be fixed capacitors.

6. The apparatus of claim 3 , further comprising at least one additional cell cascaded in series with said first half cell and said second half cell, and said signal voltage is an AC signal.

7. The apparatus of claim 3 , wherein said VVCs are voltage tunable dielectric capacitors.

8. The apparatus of claim 3 , wherein at least two dielectrics of said VVCs employ ferroelectric materials.

9. The method of claim 3 , wherein the error function is a logarithmic function of the change in the net capacitance.

10. A method comprising:

selecting using a processor, a numerical model for a tunable capacitive network, wherein the tunable capacitive network comprises a first half cell connected in parallel with a second half cell, wherein the first half cell includes a first circuit having first and second voltage variable capacitors (VVCs) configured in anti-series in which the first VVC with a same bias voltage orientation as a received signal voltage assumes a first capacitance and the second VVC with an opposite bias voltage orientation as the received signal voltage assumes a second capacitance, and wherein the second half cell includes a second circuit having third and fourth VVCs configured in anti-series in which the third VVC with the same bias voltage orientation as the received signal voltage assumes the second capacitance and the fourth VVC with the opposite bias voltage orientation as the received signal voltage assumes the first capacitance, wherein a first Direct Current (DC) feed is connected between the first VVC and the second VVC, and wherein a second DC feed is connected between the third VVC and the fourth VVC;

selecting using the processor, an error function based on a change in a net capacitance of the tunable capacitive network or its reciprocal as a function of the numerical model, a signal voltage associated with the tunable capacitive network and a bias voltage associated with the tunable capacitive network; and

selecting capacitance values for the tunable capacitive network using the processor, to reduce the error function over a desired range of the bias and signal voltages as a function of the numerical model.

11. The method of claim 10 , further comprising applying numerical methods to select the capacitance values.

12. The method of claim 10 , wherein the numerical model is associated with a capacitance-voltage curve.

13. The method of claim 10 , wherein the first half cell and the second half cell each comprise more than two VVCs.

14. The method of claim 10 , wherein at least some capacitors of the tunable capacitive network comprise thin-film dielectric material.

15. The method of claim 10 , wherein the received signal voltage is an AC voltage.

16. The method of claim 10 , wherein at least some capacitors of the tunable capacitive network are fixed capacitors.

17. The method of claim 10 , wherein the tunable capacitive network comprise resistors connected to nodes of the tunable capacitive network for connecting the nodes with at least one of a ground and a bias voltage source.

18. The method of claim 10 , wherein the tunable capacitive network comprise conductors connected to nodes of the tunable capacitive network for connecting the nodes with at least one of a ground and a bias voltage source.

19. The method of claim 10 , wherein the error function is a logarithmic function of the change in the net capacitance.

20. The method of claim 10 , wherein at least some capacitors of the tunable capacitive network comprise ferroelectric material.