Relatively low standby power

1. A circuit comprising:

a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and that generates an output signal that is an inverse of the input signal;

a first inverter that receives the output signal from the first transistor stack;

a second transistor stack that receives the voltage reference, the reference potential, the clock signal and the inverted clock signal, and that generates an output signal that is an inverse of an output signal from the first inverter; and

a pass control circuit that includes first and second transistors,

wherein first terminals of the first and second transistors are coupled together and receive the output signal of the second transistor stack, control terminals of the first and second transistors receive the clock signal and the inverted clock signal, respectively, and second terminals of the first and second transistors are coupled together and output the output signal of the second transistor stack; and

a logic circuit that receives an external clock signal and a standby signal, and that generates the clock signal.

2. A circuit, comprising:

a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and that generates an output signal that is an inverse of the input signal;

a first inverter that receives the output signal from the first transistor stack;

a second transistor stack that receives the voltage reference, the reference potential, the clock signal and the inverted clock signal, and that generates an output signal that is an inverse of an output signal from the first inverter;

a pass control circuit that includes first and second transistors,

wherein first terminals of the first and second transistors are coupled together and receive the output signal of the second transistor stack, control terminals of the first and second transistors receive the clock signal and the inverted clock signal, respectively, and second terminals of the first and second transistors are coupled together and output the output signal of the second transistor stack; and

a combinational logic circuit that generates the input signal and that is selectively powered down,

wherein the first transistor stack, the first inverter and the second transistor stack maintain a value of the input signal while the combinational logic is powered down.

3. The circuit of claim 1 , wherein the first transistor stack comprises:

a third transistor including a first terminal that receives the voltage reference, and including a control terminal that receives the inverted clock signal;

a fourth transistor including a first terminal that communicates with a second terminal of the third transistor, and including a control terminal that receives the input signal;

a fifth transistor including a second terminal that communicates with a second terminal of the fourth transistor, and including a control terminal that receives the input signal; and

a sixth transistor including a second terminal that communicates with a first terminal of the fifth transistor, a control terminal that receives the clock signal, and a first terminal that communicates with the reference potential.

4. The circuit of claim 3 , wherein the third transistor and the fourth transistor comprise p-type MOS transistors, and the fifth transistor and the sixth transistor comprise n-type MOS transistors.

5. The circuit of claim 3 , further comprising:

a second inverter that communicates with the second terminal of the fourth transistor and the second terminal of the fifth transistor,

wherein the second inverter receives an output signal from the first transistor stack, and wherein the second inverter generates an output signal.

6. The circuit of claim 1 , wherein the second transistor stack comprises:

a third transistor including a first terminal that receives the voltage reference, and including a control terminal that receives the output signal from the first inverter;

a fourth transistor including a first terminal that communicates with a second terminal of the third transistor, and including a control terminal that receives the clock signal;

a fifth transistor including a second terminal that communicates with a second terminal of the fourth transistor, and including a control terminal that receives the inverted clock signal; and

a sixth transistor including a second terminal that communicates with a first terminal of the fifth transistor, a control terminal that receives the output signal from the first inverter, and a first terminal that communicates with the reference potential.

7. The circuit of claim 6 , wherein the third transistor and the fourth transistor comprise p-type MOS transistors and the fifth transistor and the sixth transistor comprise n-type MOS transistors.

8. The circuit of claim 1 , wherein the first and second transistor stacks prevent a direct electrical path between the voltage reference and the reference potential during operation.

9. A wireless device comprising:

an antenna; and

a processing device that communicates with the antenna, wherein the processing device comprises the circuit of claim 1 .

10. The wireless device of claim 9 , wherein the wireless device comprises a cellular telephone, a cellular-enabled personal digital assistant, or a cellular-enabled automobile.