System and method for common mode calibration in an analog to digital converter
A conversion circuit increases a gain of an analog-to-digital converter (ADC) preamplifier by minimizing a common mode offset voltage between an input signal and a reference signal. The feedback controller circuit calibrates an input common mode voltage to mitigate a common mode offset voltage. Reduction of the common mode offset voltage increases the gain of the ADC preamplifier. In an example, the method is executed during a hold phase of a track-and-hold circuit that transmits the input signal to the ADC.
1. A method for improving an analog-to-digital converter (ADC) preamplifier gain, comprising:
comparing an ADC input signal to a reference voltage to determine a common mode offset voltage that is input to an ADC preamplifier; and
minimizing the common mode offset voltage to improve the ADC preamplifier gain.
2. The method of claim 1 , wherein at least one of the comparing and the minimizing occurs during a hold mode of a track-and-hold circuit providing the ADC input signal.
3. The method of claim 1 , wherein the comparing comprises:
using a calibration common mode voltage as the reference voltage;
using an input common mode voltage of the ADC input signal; and
determining a difference between the calibration common mode voltage and the input common mode voltage to determine the common mode offset voltage.
4. The method of claim 1 , further comprising using an ADC to perform the comparing.
5. The method of claim 1 , wherein the minimizing reduces the common mode offset voltage to substantially zero volts.
6. The method of claim 1 , wherein the minimizing comprises adjusting a front-end circuit.
7. The method of claim 6 , further comprising varying a voltage input to the front-end circuit.
8. The method of claim 1 , further comprising controlling the minimizing by measuring an ADC output and adjusting a front-end circuit with a feedback circuit.
9. A conversion circuit, comprising:
an analog-to-digital converter (ADC) preamplifier;
means for comparing an ADC input signal to a reference voltage to determine a common mode offset voltage that is input to the ADC preamplifier; and
means for minimizing the common mode offset voltage to improve the ADC preamplifier gain.
10. The conversion circuit of claim 9 , further comprising:
a track-and-hold circuit to provide the ADC input signal, wherein at least one of the comparing and the minimizing is performed during a hold mode of the track-and-hold circuit.
11. The conversion circuit of claim 9 , wherein the means for comparing comprises:
means for using a calibration common mode voltage as the reference voltage;
wherein the ADC input signal has an input common mode voltage; and
means for determining a difference between the calibration common mode voltage and the input common mode voltage.
12. The conversion circuit of claim 9 , wherein the means for comparing comprises an ADC.
13. The conversion circuit of claim 9 , wherein the means for minimizing is configured to reduce the common mode offset voltage to substantially zero volts.
14. The conversion circuit of claim 9 , further comprising means for adjusting a front-end circuit.
15. The conversion circuit of claim 14 , further comprising means for varying a voltage input to the front-end circuit.
16. The conversion circuit of claim 9 , further comprising:
means for measuring an ADC output with a feedback circuit; and
means for adjusting a front-end circuit with the feedback circuit to control the minimizing.
17. A conversion circuit, comprising:
an analog to digital converter (ADC) input preamplifier;
means for comparing an ADC input signal having an ADC input common mode voltage to a calibration reference voltage to determine a common mode offset voltage that is input to the ADC input preamplifier; and
means for adjusting the ADC input common mode voltage to increase the ADC input preamplifier gain by minimizing the common mode offset voltage.
18. The conversion circuit of claim 17 , further comprising:
a track-and-hold circuit to provide the ADC input signal, wherein at least one of the comparing and the minimizing is performed during a hold mode of the track-and-hold circuit.
19. The conversion circuit of claim 17 , wherein the means for comparing comprises an ADC.
20. The conversion circuit of claim 17 , wherein the means for adjusting is configured to reduce the common mode offset voltage to substantially zero volts.
21. The conversion circuit of claim 17 , further comprising means for adjusting a front-end circuit.
22. The conversion circuit of claim 21 , further comprising means for varying a voltage input to the front-end circuit.
23. The conversion circuit of claim 17 , further comprising:
means for measuring an ADC output with a feedback circuit; and
means for adjusting a front-end circuit with the feedback circuit.