Instruction and logic for performing range detection
A technique to accelerate range detection in a spline calcuation. In one embodiment, an instruction and corresponding logic are provided to perform range detection within a computer or processor.
1. An apparatus comprising:
logic to perform a range detection instruction to determine a range value for each spline polynomial corresponding to a plurality of input vector elements.
2. The apparatus of claim 1 , wherein the logic includes comparison logic to compare each element of an input vector to a corresponding limit range vector element.
3. The apparatus of claim 1 , wherein the logic includes a binary search logic to compare each element of an input vector to a corresponding limit range vector element.
4. The apparatus of claim 1 , wherein the logic includes a range vector storage to store the range value vector including the range values.
5. The apparatus of claim 4 , wherein the logic includes an input vector storage to store the input vector elements.
6. The apparatus of claim 5 , wherein the logic includes at least one coefficient vector storage to store a plurality of coefficient vector elements corresponding the input vector elements.
7. The apparatus of claim 6 , wherein the logic includes at least one offset vector storage to store a plurality of offset vector elements corresponding to the input vector elements.
8. The apparatus of claim 7 , wherein the logic includes an output vector storage to store a plurality of output vector elements corresponding to the input vector elements.
9. A computer implemented method comprising:
performing a single instruction multiple data (SIMD) range detection instruction to generate a plurality of range values corresponding to a plurality of input values of a spline function;
performing a coefficient matching operation to generate a plurality of coefficients corresponding to a plurality of polynomials corresponding to the input values of the spline function;
performing a polynomial evaluation calculation to generate a plurality of output values corresponding to the plurality of input values.
10. The method of claim 9 , wherein the SIMD range detection instruction is to cause range detection logic to generate a range vector including the plurality of range values.
11. The method of claim 10 , wherein the range detection logic includes comparison logic to compare each of the plurality of input values to a corresponding limit range vector element.
12. The method of claim 10 , wherein the logic includes a binary search logic to compare each of the plurality of input values to a corresponding limit range vector element.
13. A system comprising:
a storage to store a range detection instruction;
a processor to determine a range value for each spline polynomial corresponding to a plurality of input vector elements in response to performing the range detection instruction.
14. The system of claim 13 , wherein the processor includes comparison logic to compare each element of an input vector to a corresponding limit range vector element.
15. The system of claim 13 , wherein the processor includes a binary search logic to compare each element of an input vector to a corresponding limit range vector element.
16. The system of claim 13 , wherein the processor includes a range vector storage to store the range value vector including the range values.
17. The system of claim 16 , wherein the processor includes an input vector storage to store the input vector elements.
18. The system of claim 17 , wherein the processor includes at least one coefficient vector storage to store a plurality of coefficient vector elements corresponding the input vector elements.
19. The system of claim 18 , wherein the processor includes at least one offset vector storage to store a plurality of offset vector elements corresponding to the input vector elements.
20. A processor comprising:
a first logic to perform a range detection instruction to generate a plurality of range values corresponding to a plurality of input values of a spline function;
a second logic to perform a coefficient matching operation to generate a plurality of coefficients corresponding to a plurality of polynomials corresponding to the input values of the spline function;
a third logic to perform a polynomial evaluation calculation to generate a plurality of output values corresponding to the plurality of input values.
21. The processor of claim 20 , wherein the range detection instruction is to cause the first logic to generate a range vector including the plurality of range values.
22. The processor of claim 21 , wherein the first logic includes comparison logic to compare each of the plurality of input values to a corresponding limit range vector element.
23. The processor of claim 21 , wherein the first logic includes a binary search logic to compare each of the plurality of input values to a corresponding limit range vector element.