IP Library Granted Patent US 7,949,815
Granted Patent B2
US 7,949,815 · App. 12/290,615 · Granted May 24, 2011

Virtual heterogeneous channel for message passing

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,949,815
App. No.
12/290,615
Granted
May 24, 2011
Kind
B2
Abstract

A technique includes using a virtual channel between a first process and a second process to communicate messages between the processes. Each message contains protocol data and user data. All of the protocol data is communicated over a first channel associated with the virtual channel, and the user data is selectively communicated over at least one other channel associated with the virtual channel.

Claims (7)

1. An article comprising a machine-accessible storage medium including instructions that when executed cause a system to:

create a shared memory segment to store a synchronization block for each of a plurality of processes that execute in a message passing interface (MPI) library, wherein each synchronization block includes a wait flag to indicate that the associated process is in a wait state, a first counter to indicate a number of messages sent by the associated process to another process that have not been received, a second counter to indicate the number of connections initiated by other processes to the associated process, and a pointer to a mutex for synchronization of processes during access to the synchronization block;

transfer a message from a first process to a shared memory buffer of a second process via a shared memory connection; and

send a wake up message from the first process to the second process via a secondary connection if the second process is in the wait state.

2. The article of claim 1 , further comprising instructions that enable the system to move the message from the shared memory buffer to a user buffer of the second process.

3. The article of claim 2 , further comprising instructions that enable the system to send a wake up message from the second process to the first process if the first process is in the wait state when the second process moves the message.

4. The article of claim 3 , further comprising instructions that enable the system to de-allocate the shared memory buffer via the first process after the first process is activated from the wait state.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2009
From: SUPALOV, ALEXANDER V.; TRUSCHIN, VLADIMIR D.; RYZHYKH, ALEXEY V.
To: INTEL CORPORATION
Reel/Frame 022126/0336 →
Continuity (2)
Continuation In Part 11528201 · Sep 27, 2006
Related Publication 20090119676A1 · May 7, 2009