Semiconductor storage device
View Patent ↗A semiconductor storage device includes a memory array compartmentalized into first and second regions alternately arranged. The second regions are formed by odd and even columns alternately arranged. The semiconductor storage device includes: a memory mat array arranged in each first region; a sense amp array arranged in each second region; local IO lines arranged in each second region and connected to the sense amp array; main IO lines crossing the first and second regions; and a read/write amplifier arranged in each second region and at an intersection region where the local IO lines cross the main IO lines. The read/write amplifier in an odd column is connected to a local IO line therein and to a local IO line in the next odd column. The read/write amplifier in an even column is connected to a local IO line therein and to a local IO line in the next even column.
1. A semiconductor storage device including a memory array compartmentalized into a plurality of first regions and second regions alternately arranged, the second regions being formed by odd and even columns alternately arranged, the semiconductor storage device comprising:
a memory mat array arranged in each of the first regions;
a sense amp array arranged in each of the second regions;
local IO lines arranged in each of the second regions and connected to the sense amp array;
main IO lines crossing all of the first regions and the second regions; and
a read/write amplifier arranged in each of the second regions and at one of intersection regions where the local IO lines cross the main IO lines, wherein
the read/write amplifier in one of the odd columns is connected to a first local IO line in said one of the odd columns and to a second local IO line in next one of the odd columns, and
the read/write amplifier in one of the even columns is connected to a third local IO line in said one of the even columns and to a fourth local IO line in next one of the even columns.
2. The semiconductor storage device according to claim 1 , wherein each of the intersection regions includes one read/write amplifier.
3. The semiconductor storage device according to claim 1 , wherein the read/write amplifier comprises:
a sharing circuit that selects any one of the first local IO line and the second local IO line according to a memory-mat selection signal;
a write amp that, upon a writing phase, amplifies a signal on one of the main IO lines and outputs the amplified signal to any one of the first IO line and the second IO line that is selected by the sharing circuit; and
a read amp that, upon a reading phase, amplifies a signal on any one of the first local IO line and the second local IO line that is selected by the sharing circuit, and outputs the amplified signal to one of the main IO lines.
4. The semiconductor storage device according to claim 3 , wherein the sharing circuit that includes a plurality of transfer gates that are controlled according to the memory-mat selection signal.
5. The semiconductor storage device according to claim 4 , wherein
the transfer gates include a first pair of transfer gates connected to the first local IO line and a second pair of transfer gates connected to the second local IO line through a local IO redundant line,
the first pair of transfer gates changes to a conductive-state and the second pair of transfer gates changes to a non-conductive state so that the first local IO line is selected when the memory-mat selection signal is low, and
the first pair of transfer gates changes to a non-conductive state and the second pair of transfer gates changes to a conductive-state so that the second local IO line is selected when the memory-mat selection signal is high.
6. The semiconductor storage device according to claim 3 , wherein the write amp includes a plurality of P-channel MOS transistors and N-channel MOS transistors.
7. The semiconductor storage device according to claim 3 , wherein the read amp includes a plurality of P-channel transistors and N-channel transistors, a capacitor, an inverter, and a NOR circuit.