Processor for processing instruction set of plurality of instructions packed into single code
A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes converted by a conversion table. A plurality of ALUs perform the operation in accordance with the decoding result of the instruction decoder. Therefore, the number of instructions that can be executed in parallel per cycle may be increased while at the same time the capacity of the instruction memory is reduced.
1 - 13 . (canceled)
14 . A data processor comprising:
an instruction fetch unit;
an instruction decode unit;
an instruction execute unit; and
an instruction interpretation unit;
wherein the instruction fetch unit fetches an instruction from a memory, the instruction having at least a first part and a second part,
wherein the instruction interpretation unit interprets a binary pattern in the first part of the instruction as an instruction package containing a plurality of instructions by referring to a converting table when the second part of the instruction indicates a first status, or as a single instruction when the second part of the instruction indicates a second status,
wherein the instruction decode unit decodes each of the plurality of instructions of the instruction package interpreted by the instruction interpretation unit when the second part of the instruction indicates the first status, or decodes the single instruction when the second part of the instruction indicates the second status,
wherein the instruction execution unit executes the plurality of instructions or the single instruction decoded by the instruction decode unit, and
wherein the converting table is supplied from the outside data processor.
15 . A data processor according to claim 14 ,
wherein the instruction execute unit executes the plurality of instructions whether in serial or in parallel in accordance with a third part of the instruction.
16 . A data processor being adapted to perform each functions following:
an instruction fetching function that fetches an instruction from a memory,
an instruction interpreting function that interprets a binary pattern in a first part of the instruction as a plurality of instructions by referring a converting table when a second part of the instruction indicates a first status, or as a single instruction when the second part of the instruction indicates a second status,
an instruction decoding function that decodes each of the plurality of instructions when the second part of the instruction indicates the first status, or decodes the single instruction when the second part of the instruction indicates the second status,
an instruction executing function executes each of the plurality of instructions or the single instruction, and
a reading function that reads the converting table from outside the data processor.
17 . A data processor according to claim 16 ,
wherein the instruction execution function that executes the plurality of instructions whether in serial or in parallel in accordance with a third part of the instruction.