Electronic device and integrated circuit
View Patent ↗An electronic device with a CMOS circuit (CC) comprises a first driver circuit ( 10 ) having a first and second PMOS transistor (P 1 , P 2 ) and a first and second NMOS transistor (N 1 , N 2 ). The electronic device furthermore comprise a second driver circuit ( 20 ) with a third and fourth PMOS transistor (P 3 , P 4 ) and a third and fourth NMOS transistor (N 3 , N 4 ). The second driver circuit ( 20 ) is complementary to the first driver circuit ( 10 ) and switches in the opposite direction to the first driver circuit ( 10 ). A gate of the second and fourth PMOS transistor (P 2 , P 4 ) is coupled to a first bias voltage (REPp) and a gate of the second and fourth NMOS transistor (N 2 , N 4 ) is coupled to a second bias voltage (REFn). A first capacitance (C 3 ) is coupled between the gate and the drain of the fourth PMOS transistor (P 4 ) and a second capacitance (C 4 ) is coupled between the gate and the drain source of the fourth NMOS transistor (N 4 ).
1. Electronic device, comprising:
a CMOS circuit (CC);
a first driver circuit having a first and second PMOS transistor and a first and second NMOS transistor coupled between a first voltage (vdde) and ground, wherein the first driver circuit is coupled to the CMOS circuit (CC);
a second driver circuit having a third and fourth PMOS transistor and a third and fourth NMOS transistor coupled between the first voltage and ground;
said second driver circuit being complementary to the first driver circuit and switching in the opposite direction of the first driver circuit;
wherein a gate of the second and fourth PMOS transistor is coupled to a first bias voltage and a gate of the second and fourth NMOS transistor is coupled to a second bias voltage; and
wherein a first capacitance is coupled between a gate and a drain of the fourth PMOS transistor and a second capacitance is coupled between a gate and a source of the fourth NMOS transistor.
2. Electronic device according to claim 1 , wherein the size of the second driver circuit is smaller than the size of the first driver circuit.
3. Electronic device according to claim 2 , further comprising:
a PMOS pre-driver circuit coupled to the gate of the first PMOS transistor,
a NMOS pre-driver circuit coupled to the gate of the first NMOS transistor,
wherein the gate of the third PMOS transistor is coupled to the PMOS pre-driver circuit or is coupled to the drain of the first PMOS transistor;
wherein the gate of the third NMOS transistor is coupled to the NMOS pre-driver circuit or is coupled to the drain of the first NMOS transistor.
4. Electronic device according to claim 1 , further comprising:
a third capacitance coupled between the gate of the second PMOS transistor and ground, and
a fourth capacitance coupled between the gate of the second NMOS transistor and ground.
5. Integrated circuit, comprising:
a CMOS circuit (CC);
a first driver circuit having a first and second PMOS transistor and a first and second NMOS transistor coupled between a first voltage and ground, wherein the first driver circuit is coupled to the CMOS circuit (CC);
a second driver circuit having a third and fourth PMOS transistor and a third and fourth NMOS transistor coupled between the first voltage and ground;
said second driver circuit being complementary to the first driver circuit and switching in the opposite direction of the first driver circuit;
wherein a gate of the second and fourth PMOS transistor is coupled to a first bias voltage and a gate of the second and fourth NMOS transistor is coupled to a second bias voltage; and
wherein a first capacitance is coupled between a gate and a drain of the fourth PMOS transistor and a second capacitance is coupled between a gate and a source of the fourth NMOS transistor.
6. Transmitter comprising an electronic device according to claim 1 .