MIM capacitor integration
An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor plates to conductors in an overlying metallization layer are formed so as to contact the extension portions of the top and bottom plates. Etching of the via holes is simplified because it is permissible for the via holes to punch through the extension portions of the capacitor plates. The bottom plate of the MIM capacitor is inlaid. The top plate of the MIM capacitor may be inlaid.
1. An integrated circuit device comprising:
an upper wiring layer and a lower wiring layer, and a metal-insulator-metal (MIM) capacitor in an inter-layer dielectric layer between said upper and lower wiring layers, the MIM capacitor comprising a top plate, a bottom plate and a dielectric layer between the top and bottom plates;
wherein the MIM capacitor top plate has a region which does not face the MIM capacitor bottom plate;
wherein the MIM capacitor bottom plate has a region which does not face the MIM capacitor top plate; and
conductive vias extend from said upper wiring layer to the MIM capacitor top and bottom plates, including a conductive via contacting and extending through the MIM capacitor top plate at said region thereof which does not face the bottom plate, and a conductive via contacting and extending through the MIM capacitor bottom plate at said region thereof which does not face the top plate, said conductive via that contacts the top plate terminates at a first dielectric portion within the inter-layer dielectric layer between the MIM capacitor and the lower wiring layer, and the conductive via that contacts the bottom plate terminates at a second dielectric portion within the inter-layer dielectric layer between the MIM capacitor and the lower wiring layer.
2. The integrated circuit device according to claim 1 , wherein the MIM capacitor bottom plate is inlaid.
3. The integrated circuit device according to claim 1 , wherein the MIM capacitor top plate is inlaid.
4. A method of fabricating an integrated metal-insulator-metal (MIM) capacitor, the method comprising the steps of:
forming a MIM capacitor bottom plate over a first dielectric layer, said first dielectric layer between said MIM capacitor and a metallization layer;
forming a second dielectric layer over at least a portion of the MIM capacitor bottom plate;
forming a MIM capacitor top plate over the second dielectric layer such that there is a portion of the top plate that does not face the bottom plate and a portion of the bottom plate that does not face the top plate;
forming a third dielectric layer over the MIM capacitor top plate;
etching a first via hole through one of said top plate at said region thereof which does not face the bottom plate and said bottom plate at said region thereof which does not face the top plate;
etching a second via hole through said bottom plate at a region which does not face the top plate;
stopping the etching of the second via hole through the bottom plate in the first dielectric layer between the MIM capacitor and the metallization layer, and
stopping the etching of the first via hole at a dielectric portion of the first dielectric layer between the MIM capacitor and the metallization layer.
5. An integrated-MIM-capacitor fabrication method according to claim 4 , wherein the step of forming the MIM capacitor bottom plate comprises the step of forming an inlaid bottom plate.
6. An integrated-MIM-capacitor fabrication method according to claim 4 , wherein the step of forming the MIM capacitor top plate comprises the step of forming an inlaid top plate.
7. The integrated circuit device according to claim 2 , wherein the MIM capacitor top plate is inlaid.
8. An integrated-MIM-capacitor fabrication method according to claim 5 , wherein the step of forming the MIM capacitor top plate comprises the step of forming an inlaid top plate.
9. An integrated circuit device comprising:
a metal-insulator-metal (MIM) capacitor in a first dielectric layer, the MIM capacitor underlying an upper surface of the integrated circuit device and comprising a top plate, a bottom plate, and a second dielectric layer between the top plate and the bottom plate; and
a first conductive via in contact with and extending through the bottom plate, and the first conductive via terminating at a dielectric portion within the first dielectric layer underlying MIM capacitor.
10. An integrated circuit device according to claim 9 , further comprising a second conductive via in contact with and extending through the top plate, and the second conductive via terminating within the first dielectric layer underlying MIM capacitor.
11. An integrated circuit device according to claim 10 , wherein the MIM capacitor top plate is inlaid.
12. An integrated circuit device according to claim 11 , wherein the MIM capacitor bottom plate is inlaid.
13. An integrated circuit device according to claim 10 , wherein the MIM capacitor bottom plate is inlaid.
14. An integrated circuit device according to claim 9 , wherein the MIM capacitor top plate is inlaid.
15. An integrated circuit device according to claim 14 , wherein the MIM capacitor bottom plate is inlaid.
16. An integrated circuit device according to claim 15 , wherein the MIM capacitor bottom plate is inlaid.
17. An integrated circuit device according to claim 9 , wherein the MIM capacitor bottom plate is inlaid.