A data processor includes: a data input unit that inputs data in real time; an input data storing unit in which the inputted data is stored; a signal processing unit that reads out the stored data and performs signal processing of the stored data; a signal processing control unit that has the signal processing unit intermittently perform the signal processing faster than real-time; a clock/power source control unit that reduces power consumption by restricting a clock signal and/or electric power to the signal processing unit and the signal processing control unit in an inactive period of the intermittent operation; and an input monitor unit that monitors the volume of stored data, requests the clock/power source control unit to remove a clock or power restriction based on the volume, and requests the signal processing control unit to move into an active period of the intermittent operation.
1. A data processor comprising:
a data input unit into which data is inputted;
an input data storing unit in which said data inputted into said data input unit is stored;
a signal processing unit operable to read out said data stored in said input data storing unit, and perform signal processing of data read from said input data storing unit;
a signal processing control unit operable to control said signal processing unit to have said signal processing unit perform an intermittent operation by having said signal processing unit perform said signal processing at a processing speed faster than a speed at which said data is inputted into said data input unit;
a clock/power source control unit operable to reduce electric power consumption of said signal processing unit and said signal processing control unit by restricting either or both a clock signal and an electric power to at least one section of said signal processing unit and said signal processing control unit in an inactive period of said intermittent operation; and
an input monitor unit operable to monitor the volume of data in said input data storing unit, to request said clock/power source control unit to remove the restriction of either or both a clock signal and an electric power to at least one section of said signal processing unit and said signal processing control unit on the basis of said volume of data in said input data storing unit, and to request said signal processing control unit to move into an active period of said intermittent operation.
2. A data processor according to claim 1 , wherein
said input monitor unit makes the requests to said clock/power source control unit and said signal processing control unit when said volume of data in said input data storing unit becomes equal to or larger than a predetermined threshold level.
3. A data processor according to claim 1 , further comprising:
an output data storing unit in which said data processed by said data processing unit is stored;
a data output unit operable to read out and output data stored in said output data storing unit; and
an output monitor unit operable to monitor the volume of data in said output data storing unit, to request said clock/power source control unit to remove the restriction of either or both a clock signal and an electric power to at least one section of said signal processing unit and said signal processing control unit on the basis of said volume of data in said output data storing unit, and to request said signal processing control unit to move into an active period of said intermittent operation.
4. A data processor according to claim 3 , wherein
said output monitor unit makes the requests to said clock/power source control unit and said signal processing control unit when said volume of data in said input data storing unit becomes equal to or smaller than said predetermined threshold level.
5. A data processor according to claim 3 , wherein
said data output unit performs a digital-to-analog conversion of said data stored in said output data storing unit.
6. A data processor according to claim 1 , wherein
said data to be inputted into said data input unit is constituted by compressed data, said signal processing of data includes a data decompression.
7. A data processor according to claim 1 , wherein
said data to be inputted into said data input unit is indicative of a sound, said signal processing of data includes a sound quality conversion.
8. A data processor according to claim 1 ,
wherein said data input unit performs an analog-to-digital conversion of said inputted data.
9. A data processor according to claim 1 , wherein
said clock/power source control unit restricts said electric power consumption of said signal processing unit and said signal processing control unit by reducing a frequency of said clock signal to at least one section of said signal processing unit and said signal processing control unit.
10. A data processor according to claim 1 , wherein
said clock/power source control unit restricts said electric power consumption of said signal processing unit and said signal processing control unit by stopping supplying said clock signal to at least one section of said signal processing unit and said signal processing control unit.
11. A data processor according to claim 1 ,
wherein said clock/power source control unit reduces said electric power consumption of said signal processing unit and said signal processing control unit by reducing a voltage applied to at least one section of said signal processing unit and said signal processing control unit.
12. A data processor according to claim 1 ,
wherein said clock/power source control unit reduces said electric power consumption of said signal processing unit and said signal processing control unit by stopping applying a voltage to at least one section of said signal processing unit and said signal processing control unit.