Method and apparatus for reconfiguring IC architectures
View Patent ↗A reconfigurable hardware architecture, in the form of a System-on-Chip 1 , includes an ASIC ( 19 ) and an embedded FPGA ( 18 ) which define static and reconfigurable parts of an IC architecture ( 15 ) respectively. Incoming Ethernet, or other format, packets are applied to a packet filter ( 14 ), which detects those packets containing reconfiguration data. The reconfiguration data is used to update the FPGA ( 18 ).
1. A method for reconfiguring an integrated circuit (IC) architecture, the IC architecture having a static part and a reconfigurable part, including the steps of:
detecting each incoming packet with a packet filter to determine whether it is a reconfiguration packet including reconfiguration data or a non-reconfiguration packet;
if the packet is determined to be a non-reconfiguration packet, forwarding the non-reconfiguration packet to the static part of the IC architecture;
if the packet is determined to be a reconfiguration packet, sending to the reconfigurable part of the IC architecture reconfiguration data contained in the reconfiguration packets; and
applying reconfiguration data contained in the reconfiguration packets to reconfigure the reconfigurable part of the IC architecture.
2. The method as claimed in claim 1 and wherein the reconfiguration packets are Ethernet packets.
3. The method as claimed in claim 1 and wherein the reconfiguration packets are IP packets.
4. The method as claimed in claim 1 and including sending the reconfiguration packets in a data stream with non-reconfiguration packets.
5. The method as claimed in claim 1 and applying a Quality of Service requirement to reconfiguration packets.
6. The method as claimed in claim 1 and wherein the reconfiguration data is contained only in the payload section of the reconfiguration packets.
7. The method as claimed in claim 1 and wherein the headers of the reconfiguration packets include an indication that they are reconfiguration packets.
8. The method as claimed in claim 1 and wherein the static part of the IC architecture is an Application Specific Integrated Circuit (ASIC).
9. The method as claimed in claim 1 wherein the reconfigurable part of the IC architecture is a Field Programmable Gate Array (FPGA).
10. The method as claimed in claim 1 and wherein the reconfigurable part of the IC architecture is a Network Processor (NP).
11. The method as claimed in claim 1 wherein the reconfigurable part is embedded in the static part.
12. The method as claimed in claim 11 and wherein the IC architecture includes a Field Programmable Gate Array (FPGA) embedded in an Application Specific Integrated Circuit (ASIC).
13. The method as claimed in claim 11 and wherein the IC architecture includes a Network Processor (NP) embedded in an Application Specific Integrated Circuit (ASIC).
14. The method as claimed in claim 1 and wherein the reconfigurable part is located next to the static part.
15. The method as claimed in claim 14 and wherein the IC architecture includes an FPGA located next to an ASIC.
16. The method as claimed in claim 14 and wherein the IC architecture includes a Network Processor (NP) located next to an Application Specific Integrated Circuit (ASIC).
17. The method as claimed in claim 1 and comprising a System-on-Chip in which the IC architecture is included.
18. The method as claimed in claim 1 and including the step of forming reconfiguration packets, each including information identifying the reconfigurable part of the IC architecture and reconfiguration data associated with the identified reconfigurable part.
19. The method as claimed in claim 1 and including the step of broadcasting reconfiguration packets containing reconfiguration data.
20. The method as claimed in claim 19 and, in parallel with broadcasting reconfiguration packets, including the step of sending reconfiguration packets to a reconfiguration controller for ordering them.
21. The method as claimed in claim 1 and including the step of collecting reconfiguration packets and sorting the reconfiguration data that they contain prior to applying it to the reconfigurable part of the IC architecture.
22. The method as claimed in claim 1 and including numbering reconfiguration packets, and using the numbering to correctly order the reconfiguration data.
23. The method as claimed in claim 1 and including the IC architecture itself detecting that reconfiguration data is arriving and initiating its own update using the data.
24. The method of claim 1 , further comprising the step of:
broadcasting the reconfiguration packet in parallel with the step of sending.
25. A system including:
an IC architecture having a static part and a reconfigurable part;
a packet filter for detecting reconfiguration packets including reconfiguration data; and
a reconfiguration controller for using the reconfiguration data to reconfigure the reconfigurable part of the IC architecture;
wherein the packet filter detects each incoming packet to determine whether it is a reconfiguration packet including reconfiguration data or a non-reconfiguration packet;
if the packet is determined to be a non-reconfiguration packet, the packet filter forwards the non-reconfiguration packet to the static part of the IC architecture; and
if the packet is determined to be a reconfiguration packet, the packet filter sends to the reconfigurable part of the IC architecture reconfiguration data contained in the reconfiguration packet for reconfiguration of the reconfigurable part of the IC architecture.
26. The system as claimed in claim 25 and wherein the packet filter filters reconfiguration Ethernet packets.
27. The system as claimed in claim 25 and wherein the packet filter filters reconfiguration IP packets.
28. The system as claimed in claim 25 and wherein the static part is an Application Specific Integrated Circuit (ASIC).
29. The system as claimed in claim 25 and wherein the reconfigurable part is a Field Programmable Gate Array (FPGA).
30. The system as claimed in claim 25 and wherein the reconfigurable part is embedded in the static part.
31. The system as claimed in claim 25 and wherein the static part is located adjacent the reconfigurable part.
32. The system as claimed in claim 25 and wherein the system is a System-on-Chip.
33. The system of claim 25 , wherein the packet filter forwards the reconfiguration packet to the static part of the IC architecture in parallel with sending to the reconfigurable part of the IC architecture the reconfiguration data.
34. A network comprising a plurality of systems, each system including:
an IC architecture having a static part and a reconfigurable part;
a packet filter for detecting reconfiguration packets including reconfiguration data; and
a reconfiguration controller for using the reconfiguration data to reconfigure the reconfigurable part of the IC architecture; and
the network further comprising means for forming reconfiguration packets; and
a distributor for distributing the reconfiguration packets to the systems;
wherein the packet filter detects each incoming packet to determine whether it is a reconfiguration packet including reconfiguration data or a non-reconfiguration packet;
if the packet is determined to be a non-reconfiguration packet, the packet filter forwards the non-reconfiguration packet to the static part of the IC architecture; and
if the packet is determined to be a reconfiguration packet, the packet filter sends to the reconfigurable part of the IC architecture reconfiguration data contained in the reconfiguration packet for reconfiguration of the reconfigurable part of the IC architecture.
35. The network of claim 34 , wherein the packet filter forwards the reconfiguration packet to the static part of the IC architecture in parallel with sending to the reconfigurable part of the IC architecture the reconfiguration data.