IP Library Granted Patent US 8,493,307
Granted Patent B2
US 8,493,307 · App. 12/314,846 · Granted Jul 23, 2013

Display device

Inventors: Noboru Kataoka (Oamishirasato, JP); Fumiaki Komori (Isumi, JP); Takashi Watanabe (Kokubunji, JP); Futoshi Furuta (Kokubunji, JP); Hiroshi Kageyama (Hachioji, JP)
Assignees: Hitachi Displays, Ltd.; Panasonic Liquid Crystal Display Co., Ltd.
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Quick Facts
Patent No.
US 8,493,307
App. No.
12/314,846
Granted
Jul 23, 2013
Kind
B2
Abstract

To realize a random number generating circuit that is optimum for a liquid crystal display device that is used in a terminal device that includes a display/input component. A liquid crystal display device includes a liquid crystal display panel, a control circuit and a random number generating circuit, the random number generating circuit comprises plural shift registers, an output circuit and a register that stores an initial value, and the random number generating circuit is equipped with plural initial values, whereby the randomness of the random numbers is improved. Further, it becomes possible to increase and output frequencies by the output circuit because it is possible to output respectively different random numbers from the plural shift registers.

Claims (37)

1. A display device comprising:

a display panel;

a drive circuit driving each pixel of the display panel; and

a control circuit outputting display data to the drive circuit, wherein a random number generating circuit is disposed in the control circuit,

an output circuit n-multiplies the frequency of a pulse signal that the random number generating circuit has generated and outputs a serial random signal that has the n-multiplied frequency,

the output circuit includes n first latch circuits, n second latch circuits, and one serial output circuit, with n being an integer that is greater than one, and

wherein a radio wave intensity of the output circuit is larger than a radio wave intensity of the display data at a fundamental frequency of the display data so that the serial random signal covers a frequency band from an inverse frequency of a random sequence period to the fundamental frequency.

2. A display device according to claim 1 , wherein the random number generating circuit includes n number of shift registers.

3. A display device according to claim 1 , wherein the random number generating circuit includes a register that stores n number of initial values.

4. A display device according to claim 1 , wherein the random number generating circuit includes n number of shift registers, and the shift registers synchronize to a transfer clock of the display data.

5. A display device comprising:

a display panel;

a drive circuit driving each pixel of the display panel;

a control circuit outputting display data to the drive circuit;

a random number generating circuit is disposed in the control circuit;

a memory element storing an initial value of the random number generating circuit; and

a noise generating output circuit to which a signal that the random number generating circuit has generated is inputted, the noise generating output circuit generating an n-multiplied frequency serial random signal from n number of pulse signals, the noise generating output circuit including n first latch circuits, n second latch circuits, and one serial output circuit, n being an integer that is greater than one, and

wherein a radio wave intensity of the output circuit is larger than a radio wave intensity of the display data at a fundamental frequency of the display data so that the serial random signal covers a frequency band from an inverse frequency of a random sequence period to the fundamental frequency.

6. A display device according to claim 5 , wherein the random number generating circuit includes n number of shift registers.

7. A display device according to claim 5 , wherein the random number generating circuit includes a register that stores n number of the initial values.

8. A display device according to claim 5 , wherein the random number generating circuit includes a register that stores n number of the initial values, and the initial values are transferred from the memory element to the register.

9. A display device according to claim 5 , wherein the random number generating circuit includes n number of shift registers, and the shift registers synchronize to a transfer clock of the output data.

10. A display device comprising:

a display panel;

a touch panel being superposed on the display panel;

a drive circuit driving each pixel of the display panel;

a control circuit outputting display data to the drive circuit;

a random number generating circuit being disposed in the control circuit;

a memory element storing an initial value of the random number generating circuit; and

a noise generating output circuit to which a signal that the random number generating circuit has generated is inputted,

wherein the noise generating output circuit generates an n-multiplied frequency serial random signal from n number of pulse signals,

wherein the noise generating output circuit includes n first latch circuits, n second latch circuits, and one serial output circuit, n being an integer that is greater than one, and

wherein a radio wave intensity of the noise generating output circuit is larger than a radio wave intensity of the display data at a fundamental frequency of the display data so that the serial random signal covers a frequency band from an inverse frequency of a random sequence period to the fundamental frequency.

11. A display device according to claim 10 , wherein the random number generating circuit includes n number of shift registers.

12. A display device according to claim 10 , wherein the random number generating circuit includes a register that stores n number of the initial values.

13. A display device according to claim 10 , wherein the random number generating circuit includes a register that stores n number of the initial values, and the initial values are transferred from the memory element to the register.

14. A display device according to claim 10 , wherein the random number generating circuit includes n number of shift registers, and the shift registers synchronize to a transfer clock of the output data.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2025
From: JAPAN DISPLAY INC
To: MAGNOLIA PURPLE CORPORATION
Reel/Frame 071890/0202 →
CHANGE OF NAME Recorded Nov 17, 2023
From: HITACHI DISPLAYS, LTD.
To: JAPAN DISPLAY EAST, INC.
Reel/Frame 065614/0223 →
CHANGE OF NAME Recorded Nov 17, 2023
From: JAPAN DISPLAY EAST, INC.
To: JAPAN DISPLAY, INC.
Reel/Frame 065614/0644 →
CHANGE OF ADDRESS Recorded Nov 17, 2023
From: JAPAN DISPLAY, INC.
To: JAPAN DISPLAY, INC.
Reel/Frame 065654/0250 →
NUNC PRO TUNC ASSIGNMENT Recorded Nov 17, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 065615/0327 →
MERGER Recorded Dec 13, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027482/0140 →
ATTACHED ARE (1) THE COMPANY SPLIT DOCUMENTS IN JAPANESE WITH ENGLISH TRANSLATION THEREOF AND (2) THE CERTIFICATE OF COMPANY SPLIT DOCUMENT IN JAPANESE WITH ENGLISH TRANSLATION, WHICH TOGETHER CONVEY 50% OWNERSHIP OF THE REGISTERED PATENTS AS LISTED IN THE ATTACHED TO EACH OF THE RECEIVING PARTIES (SEE PAGE 10, EXHIBIT 2-1, SECTION 1 OF THE ENGLISH TRANSLATION OF THE COMPANY SPLIT PLAN.) Recorded Dec 13, 2011
From: HITACHI, DISPLAYS, LTD.
To: HITACHI DISPLAYS, LTD.; IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027615/0589 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2008
From: KATAOKA, NOBORU; KOMORI, FUMIAKI; WATANABE, TAKASHI; FURUTA, FUTOSHI; KAGEYAMA, HIROSHI
To: HITACHI DISPLAYS, LTD.
Reel/Frame 022058/0575 →
Priority Claims (1)
JP 2007-329501 · Dec 21, 2007 · national
Continuity (1)
Related Publication 20090160829A1 · Jun 25, 2009