Semiconductor device
View Patent ↗A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.
1. A semiconductor device comprising:
a silicon substrate;
an external connection terminal disposed on the silicon substrate;
an internal circuit region disposed on the silicon substrate;
an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, the NMOS transistor having a drain region, a channel region, a source region surrounding the drain region through the channel region, and a gate electrode whose potential is fixed to a ground potential, the external connection terminal being smaller than the drain region and being formed above the drain region; and
a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region.
2. A semiconductor device according to claim 1 ; wherein the drain region has a circular shape in plan view.
3. A semiconductor device according to claim 1 ; further comprising a shallow trench isolation structure disposed around the NMOS transistor and apart from the drain region of the NMOS transistor.
4. A semiconductor device comprising:
a silicon substrate:
an external connection terminal disposed on the silicon substrate;
an internal circuit region disposed on the silicon substrate; and
an NMOS transistor for electrostatic discharge protection provided between and connected to each of the external connection terminal and the internal circuit region, the NMOS transistor having a drain region, a channel region, a source region surrounding the drain region through the channel region, and a gate electrode having a potential fixed to a ground potential, the external connection terminal being smaller than the drain region and being formed above the drain region so as not to overlap the gate electrode.
5. A semiconductor device according to claim 4 ; wherein the drain region has a circular shape in plan view.
6. A semiconductor device according to claim 4 ; further comprising a shallow trench isolation structure disposed around the NMOS transistor and in spaced-apart relation to the drain region of the NMOS transistor.
7. A semiconductor device comprising:
a silicon substrate;
an external connection terminal disposed on the silicon substrate:
an internal circuit region disposed on the silicon substrate:
an NMOS transistor for electrostatic discharge protection provided between and connected to each of the external connection terminal and the internal circuit region, the NMOS transistor having a drain region, a source region, and a gate electrode having a potential fixed to a ground potential, the external connection terminal being smaller than the drain region and being formed above the drain region so as not to overlap the gate electrode; and
a shallow trench isolation structure disposed around the NMOS transistor and in spaced-apart relation to the drain region of the NMOS transistor.