PC architecture using fast NV RAM in main memory
Systems and methods for a PC or server architecture have been disclosed. The architecture is characterized by using non-volatile RAM modules, such as MRAM modules, for at least a part of the main memory, thus accelerating the power-on sequence of the computer. Components, which were stored in prior art either in battery backed CMOS Modules or in flash memory have been deployed in the non-volatile part of the main memory. Such components can be power-on self test codes, system configuration information, device drivers, a portion of the Operating system, and a portion or all of application programs and related application data.
1 . A PC having an accelerated power-on sequence comprising:
a CPU;
a memory controller controlling a main memory, wherein the memory controller is connected to said CPU; and
said main memory implemented using partly non-volatile RAM modules and partly volatile RAM modules, wherein the main memory is connected to said memory controller.
2 . The system of claim 1 wherein said non-volatile RAM modules are MRAM modules.
3 . The system of claim 1 wherein said volatile RAM modules are DRAM modules.
4 . The system of claim 1 wherein said main memory is consisting exclusively of non-volatile RAM.
5 . The system of claim 1 wherein power-on self test codes are stored in said non-volatile RAM module part.
6 . The system of claim 1 wherein system configuration information is stored in said non-volatile RAM module part.
7 . The system of claim 1 wherein device drivers associated with the system are stored in said non-volatile RAM module part.
8 . The system of claim 1 wherein a portion of Operating system is stored in said non-volatile RAM module part.
9 . The system of claim 1 wherein a portion of application programs used and related application data is stored in said non-volatile RAM module part.
10 . The system of claim 1 wherein all application programs used and related application data is stored in said non-volatile RAM module part.
11 . The system of claim 1 wherein said PC is replaced by a server.
12 . The system of claim 1 wherein said memory controller is adapted to control DRAM as well as MRAM modules.
13 . The system of claim 1 wherein an access to either DRAM or MRAM modules is performed by different Chip Select pins.
14 . The system of claim 1 wherein configuration parameters are moved from battery backed DRAM to MRAM modules.
15 . A method to accelerate a power-on sequence of a PC comprising the steps of:
(1) providing a memory controller and a main memory of the PC;
(2) implementing said main memory using partly non-volatile RAM modules and partly volatile RAM modules; and
(3) storing power-on self test codes in said non-volatile RAM modules.
16 . The method of claim 15 wherein said non-volatile RAM modules are MRAM modules.
17 . The method of claim 15 wherein said volatile RAM modules are DRAM modules
18 . The method of claim 15 wherein said main memory consists exclusively of non-volatile RAM modules.
19 . The method of claim 15 wherein power-on self test codes are stored in said non-volatile RAM module part.
20 . The method of claim 15 wherein system configuration information is stored in said non-volatile RAM module part.
21 . The method of claim 15 wherein device drivers associated with the system are stored in said non-volatile RAM module part.
22 . The method of claim 15 wherein a portion of Operating system is stored in said non-volatile RAM module part.
23 . The method of claim 15 wherein a portion of application programs used and related application data is stored in said non-volatile RAM module part.
24 . The method of claim 15 wherein all application programs used and related application dada is stored in said non-volatile RAM module part.
25 . The method of claim 15 wherein said PC is replaced by a server.
26 . The method of claim 15 wherein said memory controller is adapted to control DRAM as well as MRAM modules.
27 . The method of claim 15 wherein an access to either DRAM or MRAM modules is performed by different Chip Select pins.
28 . The method of claim 15 wherein configuration parameters are moved from battery backed DRAM to MRAM modules.