IP Library Granted Patent US 8,245,070
Granted Patent B2
US 8,245,070 · App. 12/317,845 · Granted Aug 14, 2012

Method for optimizing voltage-frequency setup in multi-core processor systems

Assignee: Intel Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,245,070
App. No.
12/317,845
Granted
Aug 14, 2012
Kind
B2
Abstract

A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode.

Claims (21)

1. A method comprising:

ascertaining a first plurality of processor cores from a second plurality of processor cores provided in a multi-core processor, the first plurality of processor cores being operatively switched on, wherein each processor core within the multi-core includes a frequency/voltage controller;

identifying a processor core having a lowest operating frequency from among the first plurality of processor cores; and

based on a predefined functional mode, adjusting at least one operational parameter according to predetermined voltage-frequency characteristics corresponding to the identified processor core with its frequency/voltage controller.

2. The method according to claim 1 , wherein ascertaining the first plurality of processor cores is performed upon detecting a state change in any of the first and the second plurality of processor cores.

3. The method according to claim 1 , wherein the first plurality of processor cores is ascertained when at least one of the first plurality of processor cores becomes operatively switched-off.

4. The method according to claim 1 , wherein the first plurality of processor cores is ascertained when at least one of the second plurality of processor cores becomes operatively switched-on.

5. The method according to claim 1 , wherein the predefined functional mode is one of a power optimization mode and a performance optimization mode.

6. The method according to claim 5 , wherein adjusting at least one operational parameter includes adjusting only an operating voltage in a power optimization mode.

7. The method according to claim 5 , wherein adjusting at least one operational parameter includes adjusting only an operating frequency in a performance optimization mode.

8. The method according to claim 1 , wherein adjusting at least one operational parameter includes adjusting an operating voltage and an operating frequency in a mixed mode.

9. The method according to claim 1 , wherein adjusting at least one operational parameter includes operating at a frequency higher than the adjusted operational parameter.

10. A non-transitory computer-readable storage medium having computer-executable instructions, comprising:

ascertaining a first plurality of processor cores from a second plurality of processor cores provided in a multi-core processor, the first plurality of processor cores being operatively switched on, wherein each processor core within the multi-core includes a frequency/voltage controller;

identifying a processor core having a lowest operating frequency from among the first plurality of processor cores; and

based on a predefined functional mode, adjusting at least one operational parameter according to predetermined voltage-frequency characteristics corresponding to the identified processor core with its frequency/voltage controller.

11. The non-transitory computer-readable storage medium according to claim 10 , wherein the first plurality of processor cores is ascertained when at least one of the first plurality of processor cores becomes operatively switched off.

12. The non-transitory computer-readable storage medium according to claim 10 , wherein the first plurality of processor cores is ascertained when at least one of the second plurality of processor cores becomes operatively switched on.

13. The non-transitory computer-readable storage medium according to claim 10 , wherein adjusting at least one operational parameter includes adjusting only an operating voltage in a power optimization mode.

14. The non-transitory computer-readable storage medium according to claim 10 , wherein adjusting at least one operational parameter includes adjusting only an operating frequency in a performance optimization mode.

15. The non-transitory computer-readable storage medium according to claim 10 , wherein adjusting at least one operational parameter includes operating at a frequency higher than the adjusted operational parameter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2009
From: FINKELSTEIN, LEV; ABULAFIA, YOSSI; COHEN, AVIAD; RONEN, RONNY; RAJWAN, DORON; ROTEM, EFRAIM
To: INTEL CORPORATION
Reel/Frame 022580/0469 →
Continuity (1)
Related Publication 20100169609A1 · Jul 1, 2010