Semiconductor device and manufacturing method thereof
View Patent ↗A p-type body region and an n-type buffer region are formed on an n − drift region. An n ++ emitter region and a p ++ contact region are formed on the p-type body region in contact with each other. A p ++ collector region is formed on the n-type buffer region. An insulating film is formed on the n − drift region, and a gate insulating film is formed on the n ++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p + low-resistivity region is formed in the p-type body region and surrounding the interface between the n ++ emitter region and between the p-type body region and the p ++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.
1. A manufacturing method of a semiconductor device, comprising the steps of:
forming a drift region of a first conductivity type in a semiconductor layer;
forming a body region of a second conductivity type adjacent a surface of the drift region;
forming a low-resistivity region of the second conductivity type in the body region, the low-resistivity region being lower in resistivity than the body region;
forming a first semiconductor region of the first conductivity type on a surface region of the body region;
forming a contact region on a surface region of the body region, the contact region being formed in contact with the first semiconductor region and being lower in resistivity than the body region;
forming an insulating film on the surface of the drift region;
forming a gate insulating film on the surface of the body region between the first semiconductor region and the drift region;
annealing, at 900° C. to 960° C. for 20 to 40 minutes in a nitrogen atmosphere, to repair crystal lattice disorder occurring during the forming the low-resistivity region and preventing excessive diffusion from occurring in the low resistivity region, the annealing step occurring between the forming of the low-resistivity region and the forming of the gate insulating film;
forming a gate electrode on the gate insulating film, the gate electrode being formed after the step of forming a low-resistivity region has been conducted; and
forming a first semiconductor electrode in contact with the first semiconductor region and the contact region.
2. The manufacturing method of a semiconductor device according to claim 1 , further comprising:
forming a second semiconductor region of either the first or the second conductivity type adjacent the surface of the drift region, the second semiconductor region being disposed away from the body region; and
forming a second semiconductor electrode in contact with the second semiconductor region.
3. The manufacturing method of a semiconductor device according to claim 1 , further comprising:
forming another second semiconductor region of the second conductivity type,
wherein the drift region is formed on a major surface of the another second semiconductor region.
4. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the step of forming the body region is conducted using lateral diffusion, and the step of forming the low-resistivity region is conducted using ion implantation.
5. The manufacturing method of a semiconductor device according to claim 2 , wherein
the second semiconductor region is of the second conductivity type,
the first semiconductor region is an emitter region, and the first semiconductor electrode is an emitter electrode,
the second semiconductor region is a collector region, and the second semiconductor electrode is a collector electrode, and
the step of forming the emitter region is executed after the step of forming the gate electrode.
6. The manufacturing method of a semiconductor device according to claim 2 , wherein
the second semiconductor region is of the second conductivity type,
the first semiconductor region is a source region, and the first semiconductor electrode is a source electrode,
the second semiconductor region is a drain region, and the second semiconductor electrode is a drain electrode, and
the step of forming the source region is executed after the step of forming the gate electrode.
7. The manufacturing method of a semiconductor device according to claim 3 , wherein
the first semiconductor region is an emitter region, and the first semiconductor electrode is an emitter electrode,
the second semiconductor region is a collector region, and the second semiconductor electrode is a collector electrode, and
the step of forming the collector region is executed after the step of the forming the gate electrode.
8. The manufacturing method of a semiconductor device according to claim 3 , wherein
the first semiconductor region is a source region, and the first semiconductor electrode is a source electrode,
the second semiconductor region is a drain region, and the second semiconductor electrode is a drain electrode, and
the step of forming the drain region is executed after the step of forming the gate electrode.
9. The manufacturing method of a semiconductor device according to claim 4 , wherein the step of forming the low-resistivity region includes implanting boron ions at an acceleration energy of 100 to 200 keV.
10. The manufacturing method of a semiconductor device according to claim 4 , wherein the step of forming the low-resistivity region includes implanting boron ions at a dose of 1×10 13 to 5×10 13 cm −2 .