Physical layer device having an analog SERDES pass through mode
View Patent ↗A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.
1. A data communications device, comprising:
a first serializer-deserializer (SERDES) device including a first serial port and a clock and data recovery module coupled to a receive portion of said first serial port;
a second SERDES device including a second serial port and a data serializer and clock generator module coupled to a transmit portion of said second serial port; and
a first signal path that connects said first serial port to said second serial port, bypassing said clock and data recovery module and said data serializer and clock generator module.
2. The data communications device of claim 1 , wherein said first signal path carries serial data signals between said first serial port of said first SERDES device and said second serial port of said second SERDES device.
3. The data communications device of claim 1 , wherein said first signal path is coupled between a first node in said first SERDES device and a second node in said second SERDES device, said first node defined between an output of said receive portion of said first serial port and an input of said clock and data recovery module, said second node defined between an input of said transmit portion of said second serial port and an output of said serializer and clock generator module.
4. The data communications device of claim 3 , further comprising a second signal path coupled between an output of said clock and data recovery module and an input of said data serializer and clock generator module.
5. The data communications device of claim 4 , wherein said second signal path is coupled between a third node in said first SERDES device and a fourth node in said second SERDES device, said third node defined between an output of said clock and data recovery module and a digital portion of said first SERDES device, said fourth node defined between an input of said serializer clock generator and a digital portion of said second SERDES device.
6. The data communications device of claim 1 , wherein said data communications device is part of a network device.
7. The data communications device of claim 1 , wherein said data communications device is part of a data switch operating in a network environment.
8. The data communications device of claim 1 , wherein said first serial port interfaces with a network device.
9. The data communications device of claim 8 , wherein said network device includes a media access controller.
10. The data communications device of claim 8 , wherein said network device is a Ethernet device.
11. The data communications device of claim 1 , wherein said second serial port interfaces with a fiber module.
12. The data communications device of claim 1 , wherein:
said first serial port interfaces with a media access controller;
said second serial port interfaces with a fiber module.
13. The physical layer device of claim 1 , wherein said first SERDES device, said second SERDES device, and said first signal path are disposed on a common substrate.
14. The physical layer device of claim 13 , wherein said common substrate is a CMOS substrate.
15. The data communications device of claim 1 , wherein said data communications device forms part of a local communications node, and wherein said first and second SERDES devices are located on a common integrated circuit substrate at said local communications node.
16. On a substrate having a first SERDES device and a second SERDES device, said first SERDES device including a first serial port and a clock and data recovery module coupled to a receive portion of said first serial port, said second SERDES device including a second serial port and a data serializer and clock generator module coupled to a transmit portion of said second SERDES device, a method comprising:
receiving serial data from a first network device at said first serial port of said first SERDES device; and
routing said serial data from said serial port of said first SERDES device to a second serial port of said second SERDES device, and bypassing said clock and data recovery module.
17. The method of claim 16 , wherein said step of routing includes the step of bypassing said data serializer and clock generation module.
18. A data communications device, comprising:
a first serializer-deserializer (SERDES) device including a first serial port and a clock and data recovery module coupled to a receive portion of said first serial port;
a second SERDES device including a second serial port and a data serializer and clock generator module coupled to a transmit portion of said second serial port; and
means for routing serial data signals between said first serial port of said first SERDES device and said second serial port of said second SERDES device, bypassing said clock and data recovery module.
19. The data communications device of claim 18 , wherein said data communications device forms part of a local communications node, and wherein said first and second SERDES devices are located on a common integrated circuit substrate at said local communications node.