High Q and low stress capacitor electrode array
View Patent ↗An embodiment of the present invention provides a method, comprising breaking an electrode into subsections with signal bus lines connecting said subsections and a solid electrode to improve Q.
1. A method of forming a plurality of capacitors, the method comprising:
obtaining a first solid electrode formed from a first material having a first resistance;
separating a second electrode into subsections, the second electrode subsections being formed of a second material having a second resistance that is less than the first resistance;
positioning a voltage tunable dielectric material between the first solid electrode and the second electrode subsections;
connecting a first signal bus line with a first portion of the second electrode subsections thereby forming a first group of capacitors that are in parallel;
connecting a second signal bus line with a second portion of the second electrode subsections thereby forming a second group of capacitors that are in parallel;
wherein the first and second groups of capacitors are in series, and wherein the first signal bus line is selectively electrically isolated from the second signal bus line by the first and second groups of capacitors.
2. The method of claim 1 , comprising connecting the plurality of capacitors to a common tuning voltage source.
3. The method of claim 1 , wherein the voltage tunable dielectric material comprises barium strontium titanate.
4. The method of claim 1 , wherein the voltage tunable dielectric material comprises magnesium.
5. The method of claim 1 , wherein the voltage tunable dielectric material comprises at least two metal oxides.
6. The method of claim 5 , wherein the at least two metal oxides are between 1 and 80 weight percent of the voltage tunable dielectric material.
7. The method of claim 1 , wherein the voltage tunable dielectric material comprises at least two metal oxides that are magnesium free.
8. The method of claim 1 , wherein the plurality of capacitors is two capacitors.
9. A method comprising:
obtaining a first solid electrode formed from a first material having a first resistance;
separating a second electrode into subsections, the second electrode subsections being formed of a second material having a second resistance that is less than the first resistance;
positioning a voltage tunable dielectric material between the first solid electrode and the second electrode subsections; and
connecting the second electrode subsections with first and second signal bus lines thereby forming a plurality of capacitors, wherein the first signal bus line is selectively electrically isolated from the second signal bus line by the plurality of capacitors.
10. The method of claim 9 , wherein the voltage tunable dielectric material comprises magnesium.
11. The method of claim 10 , comprising connecting the plurality of capacitors to a common tuning voltage source, wherein at least a portion of the plurality of capacitors are in series, and wherein the voltage tunable dielectric material comprises barium strontium titanate and at least two metal oxides.
12. The method of claim 11 , wherein the at least two metal oxides are between 1 and 80 weight percent of the voltage tunable dielectric material.
13. The method of claim 12 , wherein a portion of the plurality of capacitors is in parallel.
14. The method of claim 11 , wherein the at least two metal oxides are magnesium free.
15. The method of claim 11 , wherein the plurality of capacitors is two capacitors.
16. A method comprising:
forming a first solid electrode having a first resistance;
forming a second electrode into subsections having a second resistance that is less than the first resistance;
positioning a voltage tunable dielectric material between the first solid electrode and the second electrode subsections; and
connecting a first bus line to a first portion of the second electrode subsections and a second bus line to a second portion of the second electrode subsections thereby forming a plurality of capacitors, wherein at least a portion of the plurality of capacitors are in series, and wherein the first bus line is selectively electrically isolated from the second bus line by the plurality of capacitors.
17. The method of claim 16 , wherein a portion of the plurality of capacitors is in parallel.
18. The method of claim 16 , comprising connecting the plurality of capacitors that are in series to a common tuning voltage source.
19. The method of claim 16 , wherein the first and second portions of the second electrode subsections are positioned in alternating rows.
20. The method of claim 19 , wherein each row of the alternating rows comprises capacitors that are in parallel.