Thin film transistor array panel
View Patent ↗A thin film transistor array panel is provided according to one or more embodiments. In an embodiment, the thin film transistor array panel includes: a base substrate that has a display area and a peripheral area; a plurality of thin film transistors that are formed in the display area; a plurality of signal input pads that are formed in the peripheral area and that are formed long in a first direction; and a plurality of signal lines that are connected to the thin film transistors and the signal input pads, wherein at least a part of each of the plurality of signal input pads is arranged in a line along the first direction.
1. A thin film transistor array panel comprising:
a base substrate that has a display area and a peripheral area;
a plurality of thin film transistors that are formed in the display area;
a plurality of signal input pads that are formed in the peripheral area and that are more elongated in a first direction than a second direction substantially perpendicular to the first direction; and
a plurality of signal lines that are connected to the thin film transistors and to the signal input pads,
wherein at least a part of the plurality of signal input pads in the first direction is aligned with each other, and at least two of the plurality of signal input pads in the second direction have different length in the first direction and
direction, wherein the plurality of signal lines extend in the second direction in the display area, and wherein the signal input pads and pad block region are elongated in the same direction.
2. The thin film transistor array panel of claim 1 , wherein at least a part of the plurality of signal input pads is sequentially arranged along the second direction.
3. The thin film transistor array panel of claim 2 , wherein the plurality of signal input pads is arranged at a predetermined interval in the first direction and at a predetermined interval in the second direction within a pad block region, and
a length of the pad block region in the first direction is longer than a length thereof in the second direction.
4. The thin film transistor array panel of claim 2 , wherein the plurality of signal input pads is formed in a plurality of pad block regions,
a distance between adjacent pad blocks is greater than a distance between two of the input signal pads adjacent in the first direction within each of the pad block regions, and
a length of each pad block region in the first direction is longer than a length thereof in the second direction.
5. The thin film transistor array panel of claim 1 , wherein the plurality of signal input pads is disposed adjacent to an edge of the base substrate parallel to the first direction.
6. The thin film transistor array panel of claim 1 , wherein each thin film transistor has a gate electrode, a source electrode, and a drain electrode, and
the signal lines are connected to the source electrodes of the thin film transistors.
7. The thin film transistor array panel of claim 1 , wherein each thin film transistor has a gate electrode, a source electrode, and a drain electrode, and
the signal lines are connected to the gate electrodes of the thin film transistors.
8. The thin film transistor array panel of claim 1 , further comprising a passivation layer that is formed on the signal lines and a part of the signal input pads.
9. The thin film transistor array panel of claim 1 , wherein the base substrate is flexible.
10. A thin film transistor array panel comprising:
a base substrate;
a plurality of thin film transistors that are formed on the base substrate;
a plurality of signal input pads that are disposed adjacent to an edge of the base substrate and are elongated in a first direction parallel to the edge of the base substrate, wherein a pad block region where the plurality of signal input pads are arranged is elongated parallel to the edge of the base substrate; and
a plurality of signal lines that are connected to the thin film transistors and the signal input pads, wherein at least two of the signal input pads have a different length in a same direction, and wherein the signal input pads and the pad block region are elongated in the same direction.
11. The thin film transistor array panel of claim 10 , wherein the plurality of signal input pads is sequentially arranged along the first direction and along a second direction substantially perpendicular to the first direction.
12. The thin film transistor array panel of claim 11 , wherein the plurality of signal input pads is arranged at a predetermined interval in the first direction and at a predetermined interval in the second direction within a pad block region, and
a length of the pad block region in the first direction is longer than a length thereof in the second direction.
13. The thin film transistor array panel of claim 11 , wherein the plurality of signal input pads is formed in a plurality of pad block regions,
a distance between adjacent pad blocks is greater than a distance between two of the input signal pads adjacent in the first direction within each pad block region, and
a length of each pad block region in the first direction is longer than a length thereof in the second direction.
14. The thin film transistor array panel of claim 10 , wherein the plurality of signal lines extends in a second direction in the display area.
15. The thin film transistor array panel of claim 10 , wherein each thin film transistor has a gate electrode, a source electrode, and a drain electrode, and
the signal lines are connected to the source electrodes of the thin film transistors.
16. The thin film transistor array panel of claim 10 , wherein each thin film transistor has a gate electrode, a source electrode, and a drain electrode, and
the signal lines are connected to the gate electrodes of the thin film transistors.
17. The thin film transistor array panel of claim 10 , further comprising a passivation layer that is formed on the signal lines and a part of the signal input pads.
18. The thin film transistor array panel of claim 10 , wherein the base substrate is flexible.
19. A thin film transistor array panel comprising:
a base substrate that has a display area and a peripheral area;
a plurality of thin film transistors that are formed on the display area;
a plurality of signal input pads that are disposed in the peripheral area and are elongated in a first direction; and wherein at least two of the signal input pads have a different length in the first direction;
a plurality of signal lines that are connected to the thin film transistors and the signal input pads and that extend in a second direction substantially perpendicular to the first direction in the display area, and wherein the signal input pads and the pad block region are elongated in the same direction.
20. The thin film transistor array panel of claim 19 , wherein the plurality of signal input pads is sequentially arranged along the first direction and along the second direction.
21. The thin film transistor array panel of claim 20 , wherein the plurality of signal input pads is arranged at a predetermined interval in the first direction and at a predetermined interval in the second direction within a pad block region, and
a length of the pad block region in the first direction is longer than a length thereof in the second direction.
22. The thin film transistor array panel of claim 20 , wherein the plurality of signal input pads is formed in a plurality of pad block regions,
a distance between adjacent pad blocks is greater than a distance between two of the input signal pads adjacent in the first direction within each pad block region, and
a length of each pad block region in the first direction is longer than a length thereof in the second direction.
23. The thin film transistor array panel of claim 19 , wherein each thin film transistor has a gate electrode, a source electrode, and a drain electrode, and
the signal lines are connected to the source electrodes of the thin film transistors.
24. The thin film transistor array panel of claim 19 , wherein each thin film transistor has a gate electrode, a source electrode, and a drain electrode, and
the signal lines are connected to the gate electrodes of the thin film transistors.
25. The thin film transistor array panel of claim 19 , further comprising a passivation layer that is formed on the signal lines and a part of the signal input pads.
26. The thin film transistor array panel of claim 19 , wherein the base substrate is flexible.