IMPLEMENTATION OF A RAPID ARITHMETIC BINARY DECODING SYSTEM OF A SUFFIX LENGTH

1 . A system for the parallel processing of a number of binstream bins comprising:

a. inputs for receiving the codIOffset, the codIRange and the bitstream suffix bits;

b. a first circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing an indication of the binstream suffix length magnitude;

c. a second circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing said number of speculative codIOffsets;

d. a third circuit for combining the products of said first circuit and the products of said second circuit for producing a new codIOffset; and

e. a fourth circuit for combining the products of said first circuit with said number of constants for producing a number indicative of the binstream suffix length.

2 . A system according to claim 1 , where the number of bitstream suffix bits is 16.

3 . A system according to claim 1 , where the binstream suffix length belongs to a syntax element of a DUCT coefficient type.

4 . A system according to claim 1 , where the binstream suffix length belongs to a syntax element of a Motion Vector.

5 . A system according to claim 1 , where the system is also used for finding errors in the bitstream suffix bits.

6 . A system according to claim 1 , where the bitstream suffix bits are fed in a terraced form into the inputs.

7 . A system according to claim 1 , where the first circuit comprises:

a. inputs for receiving the codIOffset, the codIRange and said bitstream suffix bits;

b. at least one concatenator for concatenating at least one bit of said bitstream suffix to said codIOffset;

c. at least one multiplier for multiplying said codIRange by a preset constant;

d. at least one comparator for comparing products of said concatenator and said multiplier; and

e. at least one output for outputting at least one result of said at least one comparator.

8 . A system according to claim 7 , where the first circuit further comprises:

a. at least one inverter for inverting at least one output of said first circuit; and

b. at least one AND gate for logically ANDing at least two outputs of said first circuit.

9 . A system according to claim 8 , where the system is also used for finding errors, in the bitstream suffix bits, by finding that the outputs of the AND gates have more than one logical ‘1’.

10 . A system according to claim 7 , where the preset constant is equal to the result of the function (2 i+1 −1) where i is a whole number which starts from 0 for the first input and increases by 1 for each new input.

11 . A system according to claim 7 , where the bitstream suffix bits are fed in a terraced form into the inputs.

12 . A system according to claim 1 , where the second circuit comprises:

a. inputs for receiving the codIOffset, the codIRange and said bitstream suffix bits;

b. at least one concatenator for concatenating at least one bit of said bitstream suffix to said codIOffset;

c. at least one multiplier for multiplying said codIRange by a preset constant;

d. at least one subtractor for subtracting the product of said multiplier from said concatenator; and

e. at least one output for outputting at least one result of said at least one subtractor.

13 . A system according to claim 12 , where the bitstream suffix bits are fed in a terraced form into the inputs.

14 . A system according to claim 12 , where the preset constant is equal to the result of the function (2 i+1 −2) where i is a whole number which starts from 0 for the first input and increases by 1 for each new input.

15 . A system for the parallel processing of a binstream suffix length in parts comprising:

a. inputs for receiving the codIOffset, the codIRange and the bitstream suffix bits;

b. a first circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing an indication of the binstream suffix length magnitude;

c. a second circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing said number of speculative codIOffsets;

d. a third circuit for combining the products of said first circuit and the products of said second circuit for producing a new codIOffset;

e. a fourth circuit for combining the products of said first circuit with said number of constants for producing a binstream suffix length;

f. a fifth circuit for subtracting said codIRange from the last output of the second circuit for producing a codIOffset ready for input for said first circuit and said second circuit of the next part; and

g. a sixth circuit for detecting if one of the outputs of said first circuit is a logical ‘1’.

16 . A system according to claim 15 , where the fifth circuit comprises:

a. an input for receiving the codIRange;

b. an input for receiving the last codIOffset output from the second circuit;

c. a subtractor for subtracting said codIRange from codIOffset; and

d. an output for outputting the result from said subtractor as a codIOffset for the next part of said parallel processing of said system.

17 . A system according to claim 15 , where the system is also used for finding errors in the bitstream suffix bits,

18 . A system according to claim 15 , where the bitstream suffix bits are fed in a terraced form into the inputs.

19 . A system according to claim 15 , where the sixth circuit is used for error detecting.