Digital sigma-delta modulators

1. A digital sigma-delta modulator for modulating a digital input signal (x) comprising:

a quantizer for quantizing a sum signal (s) and producing a quantized output signal (y) at a first output and an error output signal (−q) at a second output;

at least one feedback loop connected to an input adder and to at least one of the first output or the second output of the quantizer;

whereby the input adder produces the sum signal (s) by adding the digital input signal (x) at an input and output signals of the at least one feedback loop; and

a feedback filter in the at least one feedback loop, whereby the digital sigma-delta modulator is constructed as a systolic array.

2. The digital sigma-delta modulator according to claim 1 , wherein the at least one feedback loop is an error feedback loop connected to the input of the adder and the second output of the quantizer and the error feedback loop comprises an error feedback filter having a filter transfer function G m (z).

3. The digital sigma-delta modulator of claim 2 wherein the filter transfer function G m (z) has the form G m (z)=g 1 z −1 +g 2 z −2 + . . . +g m z −m and wherein the coefficients g j for all j=1,2, . . . , m are given by the equation g j =d j 2 −j+1 where all d j are arbitrary integers.

4. The digital sigma-delta modulator of claim 3 , wherein the coefficients g 1 , g 2 , . . . , g m of the filter transfer function G m (z) are realised by wired bit-shifts in a systolic array.

5. The digital sigma-delta modulator according to claim 1 , wherein the at least one feedback loop is a signal feedback loop connected to the input of the adder and the first output of the quantizer and the signal feedback loop comprises a signal feedback filter having a filter transfer function H k (z).

6. The digital sigma-delta modulator of claim 5 wherein the filter transfer function H k (z) has the form H k (z)=h 1 z −1 +h 2 z −2 + . . . +h k z −k and wherein the coefficients h j for all j=1,2, . . . , k are given by the equation h j =d j 2 −j+1 where all d j are arbitrary integers.

7. The digital sigma-delta modulator of claim 5 wherein the coefficients h 1 , h 2 , . . . , h k are realized by wired bit-shifts in a systolic array.

8. The digital sigma-delta modulator of claim 1 , wherein the at least one feedback filter comprises a plurality of adders and flip-flops (FF).

9. The digital sigma-delta modulator of claim 1 wherein the quantizer comprises a wired unity gain mid-rise quantizer.

10. The digital sigma-delta modulator of claim 9 wherein correction terms are added to the output signal (y′) and to the error signal (−q′) of the internal wired quantizer by wired bit manipulation.

11. The digital sigma-delta modulator of claim 1 wherein the quantizer comprises a wired unity gain mid-treat quantizer.

12. The digital sigma-delta modulator of claim 11 , wherein correction terms are added to the input signal (s) of the mid-treat quantizer and to the error signal (−q′) of the internal wired quantizer by wired bit manipulation.

13. The digital sigma-delta modulator of claim 1 operating in the frequency range between 0.4 and 12 GHz.

14. The digital sigma-delta modulator of claim 1 wherein the input signal (x) is a radio signal transmitted in a mobile communication network.

15. An digital-to-analog converter having a digital sigma-delta modulator of claim 1 .

16. A computer program product embodied on a computer-readable medium and comprising executable instructions for the manufacture of the digital sigma-delta modulator of claim 1 .

17. A digital sigma-delta modulator for modulating a digital input signal (x) comprising:

a quantizer for quantizing a sum signal (s) and producing a quantized output signal at a first output (y) and an error output signal (−q) at a second output;

an input adder;

a systolic array connected to the input adder at an input side of the systolic array and to the quantizer at an output side of the systolic array;

at least one feedback connection between the quantizer and at least one of the input adder or the systolic array.

18. The digital sigma-delta modulator of claim 17 , wherein the systolic array comprises a digital filter for modulator feedback.