A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.
1. A latch circuit comprising:
a feedback circuit including two first input terminals, a first output terminal, and at least one signal-output-circuit having two second input terminals and a second output terminal, the signal-output-circuit outputting second output-signal from the second output terminal, only when logic signals having same logic level are input to the two second input terminals; and
an input circuit inputting signals having same phase to the two first input terminals of the feedback circuit in synchronization with a clock signal; wherein,
in the feedback circuit, positive feedback using a certain number of amplification stages is applied to the first input terminals, and
the first output terminal is coupled to the second output terminal of the at least one signal-output-circuit
at least one of the two first input terminals is coupled to at least one of the two second input terminals of the at least one signal-output-circuit.
2. The latch circuit according to claim 1 , wherein the certain number of amplification stages is two.