Thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, which includes: forming a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor on a substrate; forming a first passivation layer on the drain and the source electrodes; forming a transparent conductive layer on the first passivation layer; etching the transparent conductive layer using a photoresist as an etch mask to expose the portion of the first passivation layer and to form a pixel electrode connected the drain electrode; ashing the first passivation layer and the photoresist; and removing the photoresist.
1. A thin film transistor array panel comprising:
an insulating substrate;
a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor and formed on the insulating substrate;
a first passivation layer on the drain and the source electrodes, and including a first contact hole and an upper surface; and
a pixel electrode formed on the first portion of the first passivation layer and connected to the drain electrode through the first contact hole,
wherein
a first portion of the upper surface is under the pixel electrode,
a second portion of the upper surface is lower than the first portion and overlaps the gate electrode,
a third portion of the upper surface is inclined with respect to the first and second portions, and connects the first portion to the second portion, such that the first and second portions are spaced apart from each other in a direction parallel to the insulating substrate, and
the pixel electrode does not overlap the third portion.
2. The thin film transistor array panel of claim 1 , wherein the first passivation layer includes an organic material.
3. The thin film transistor array panel of claim 1 , wherein the first passivation layer has photosensitivity.
4. The thin film transistor array panel of claim 1 , further comprising:
a second passivation layer formed under the first passivation layer, and
a second contact hole located at the position corresponding to the first contact hole.
5. The thin film transistor array panel of claim 4 , wherein the second passivation layer includes silicon nitride.
6. The thin film transistor array panel of claim 1 , wherein the semiconductor include extrinsic semiconductor and intrinsic semiconductor.
7. The thin film transistor array panel of claim 1 , further comprising a storage electrode line formed the same layer as the gate electrode.