Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device and a method for manufacturing the same includes forming a via pattern having a matrix form in a dielectric layer. The via pattern includes a via slit provided at the center of the via pattern and a plurality of via holes provided at an outer periphery of the via pattern and surrounding the via slit. Metal plugs are formed in the via holes.
1. A method comprising:
forming a first dielectric layer over a semiconductor substrate; and then
forming lower metal wiring over the first dielectric layer; and then
forming a second dielectric layer over the entire surface of the first dielectric layer including the lower metal wiring; and then
forming a via pattern including a plurality of via holes penetrating through the second dielectric layer and a plurality of via slits to space neighboring via holes apart from each other; and then
forming metal plugs in the via holes,
wherein the plurality of via slits are arranged in a zigzag pattern such that the plurality of via slits alternate with each other,
wherein the via pattern is formed in a matrix, the matrix has a rectangular cross section, the width of each via slit is equal to a total combined width of at least five via holes, and a height of each via slit is equal to a total combined length of at least one via hole.
2. The method of claim 1 , wherein forming the metal plugs comprises feeding a tungsten source gas in the via holes.
3. The method of claim 1 , further comprising, after forming the metal plugs:
forming upper metal wiring over the second dielectric layer and electrically connected to the lower metal wiring via the metal plugs.
4. The method of claim 1 , wherein each one of the via slits has a rectangular cross section.
5. The method of claim 2 , wherein the tungsten source gas comprises WF 6 .
6. A device comprising:
a gate pattern formed over a semiconductor substrate;
source/drain regions formed at opposite sides of the gate pattern;
a dielectric layer formed over the semiconductor substrate including the gate pattern and the source/drain regions;
a via pattern including a plurality of via holes penetrating through the dielectric layer and a plurality of via slits to space neighboring via holes apart from each other;
metal plugs formed in the via holes connected to the gate pattern and the source/drain regions;
metal wiring formed over the dielectric layer and electrically connected to the gate pattern and the source/drain regions via the metal plugs,
wherein the plurality of via slits are arranged in a zigzag pattern such that the plurality of via slits alternate with each other,
wherein the width of each via slit is equal to a total combined width of at least five via holes and a height of each via slit is equal to a total combined length of at least one via hole.
7. The device of claim 6 , wherein the metal plugs are composed of a tungsten-base material.
8. The device of claim 6 , wherein the tungsten-base material comprises WF 6 .
9. The device of claim 6 , wherein each one of the via slits has a rectangular cross section.
10. The device of claim 6 , wherein the via pattern is formed in a matrix.
11. The device of claim 10 , wherein the matrix comprises a rectangular matrix.
12. The device of claim 11 , wherein the width of each via slit is equal to a total combined widths of at least five via holes and a height of each via slit is equal to a total combined length of at least via hole.
13. The device of claim 11 , wherein via slits of neighboring rows in the matrix are arranged in the zigzag pattern.
14. The device of claim 11 , wherein via slits of neighboring columns in the matrix are arranged in the zigzag pattern.