IP Library Granted Patent US 8,166,365
Granted Patent B2
US 8,166,365 · App. 12/326,933 · Granted Apr 24, 2012

Cycle slip location and correction

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Quick Facts
Patent No.
US 8,166,365
App. No.
12/326,933
Granted
Apr 24, 2012
Kind
B2
Abstract

Methods and techniques are disclosed for correcting the effect of cycle slips in a coherent communications system. A signal comprising SYNC bursts having a predetermined periodicity and a plurality of known symbols at predetermined locations between successive SYNC bursts is received. The received signal is partitioned into data blocks. Each data block encompasses at least data symbols and a set of check symbols corresponding to the plurality of known symbols at predetermined locations between a respective pair of successive SYNC bursts in the signal. Each data block is processed to detect a cycle slip. When a cycle slip is detected, the set of check symbols of the data block are examined to identify a first slipped check symbol, and a phase correction applied to data symbols of the data block lying between the first slipped check symbol and an end of the data block.

Claims (31)

1. A method of correcting an effect of cycle slips in an optical communications system, the method comprising steps of:

receiving an optical signal through the communications system, the signal comprising SYNC bursts having a predetermined periodicity and a plurality of known symbols at predetermined locations between successive SYNC bursts;

partitioning the received optical signal into data blocks, wherein each data block encompasses at least data symbols and a set of check symbols corresponding to the plurality of known symbols at predetermined locations between a respective pair of successive SYNC bursts in the optical signal;

processing each data block to detect a cycle slip, and, when a cycle slip is detected:

examining the set of check symbols of the data block to identify a first slipped check symbol; and

applying a phase correction to data symbols of the data block lying between the first slipped check symbol and an end of the data block.

2. The method of claim 1 wherein examining the set of check symbols of the data block to identify the first slipped check symbol comprises steps of:

for each check symbol:

applying a common phase rotation to the check symbols of the data block starting at the check symbol and extending to the end of the data block; and

computing an error rate across at least the phase rotated check symbols, and associating the calculated error rate with the check symbol; and

identifying the first slipped check symbol as the check symbol associated with the lowest calculated error rate.

3. The method of claim 1 wherein the first slipped check symbol is a first check symbol in a continuous sequence of errored check symbols extending from the first slipped check symbol to the last check symbol of the data block.

4. The method of claim 3 wherein examining the set of check symbols of the data block to identify the first slipped check symbol comprises steps of:

examining each check symbol in turn, starting at the last check symbol and progressing towards a leading check symbol of the data block, until a first correct check symbol is found; and

identified a check symbol immediately following the first correct check symbol as the first slipped check symbol.

5. A coherent receiver for receiving an optical signal through an optical communications system, the coherent receiver comprising:

a detector for receiving the optical signal, the optical signal comprising SYNC bursts having a predetermined periodicity and a plurality of known symbols at predetermined locations between successive SYNC bursts;

a framer for partitioning the received optical signal into data blocks, wherein each data block encompasses at least data symbols and a set of check symbols corresponding to the plurality of known symbols at predetermined locations between a respective pair of successive SYNC bursts in the optical signal;

a decoder processing each data block to detect a cycle slip; and,

a post processor responsive to the decoder, for processing a data block affected by a cycle slip, the post processor implementing steps of:

examining the set of check symbols of the affected data block to identify a first slipped check symbol; and

applying a phase correction to data symbols of the affected data block lying between the first slipped check symbol and an end of the affected data block.

6. The coherent receiver of claim 5 wherein the first slipped check symbol is a first check symbol in a continuous sequence of errored check symbols extending from the first slipped check symbol to the last check symbol of the affected data block.

7. The coherent receiver of claim 6 wherein examining the set of check symbols of the data block to identify the first slipped check symbol comprises:

examining each check symbol in turn, starting at the last check symbol and progressing towards a leading check symbol of the data block, until a first correct check symbol is found; and

identified a check symbol immediately following the first correct check symbol as the first slipped check symbol.

8. The coherent receiver of claim 5 wherein examining the set of check symbols of the data block to identify the first slipped check symbol comprises:

for each check symbol:

applying a common phase rotation to the check symbols of the data block starting at the check symbol and extending to the end of the data block; and

computing an error rate across at least the phase rotated check symbols, and associating the calculated error rate with the check symbol; and

identifying the first slipped check symbol as the check symbol associated with the lowest calculated error rate.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2023
From: BANK OF AMERICA, N.A.
To: CIENA CORPORATION
Reel/Frame 065630/0232 →
PATENT SECURITY AGREEMENT Recorded Nov 8, 2019
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 050969/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 30, 2019
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: CIENA CORPORATION
Reel/Frame 050938/0389 →
PATENT SECURITY AGREEMENT Recorded Jul 16, 2014
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 033347/0260 →
SECURITY INTEREST Recorded Jul 15, 2014
From: CIENA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 033329/0417 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2010
From: CIENA LUXEMBOURG S.A.R.L.
To: CIENA CORPORATION
Reel/Frame 024252/0060 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2010
From: NORTEL NETWORKS LIMITED
To: CIENA LUXEMBOURG S.A.R.L.
Reel/Frame 024213/0653 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2008
From: HARLEY, JAMES; ROBERTS, KIM B.; SUN, HAN
To: NORTEL NETWORKS LIMITED
Reel/Frame 021917/0636 →