Semiconductor device and method of manufacturing the same

1. A method of manufacturing a semiconductor device, comprising:

forming, on a surface of a semiconductor substrate, a plurality of active regions of a first conductive type isolated from one another by shallow-trench isolation regions;

forming a plurality of silicon pillars including channel silicon pillars in the active regions with a silicon nitride film as a mask;

forming first semiconductor regions of a second conductive type on bottom ends of the silicon pillars with the silicon nitride film remaining on the silicon pillars;

forming a sacrificial insulating film by spin coating over the silicon pillars and the semiconductor substrate;

removing the sacrificial insulating film on circumferences of the silicon pillars excluding the channel silicon pillars;

forming capacitance-increase-prevention insulating films on portions where the sacrificial insulating film is removed to form gate-voltage-supply silicon pillars;

removing residuals of the sacrificial insulating film;

forming gate insulating films on circumferences of the channel silicon pillars;

forming gate voltage-supply electrodes surrounding the capacitance-increase-prevention insulating films, and gate electrodes surrounding the gate insulating films so that the gate voltage-supply electrodes and the gate electrodes are connected;

forming a first inter-layer insulating film over the gate voltage-supply electrodes and the gate electrodes;

removing the silicon nitride film on a top end of at least one of the channel silicon pillars so as to expose the one of the channel silicon pillars;

lowering a height of the one of the channel silicon pillars by etching;

exposing top ends of the channel silicon pillars excluding the one of the channel silicon pillars; and

forming second semiconductor regions of the second conductive type on the exposed top ends of the channel silicon pillars.

2. The method according to claim 1 , further comprising:

forming epitaxial silicon layers on the second semiconductor regions;

forming a second inter-layer insulating film over the first inter-layer insulating film and the epitaxial silicon layers;

forming contact plug holes on the first inter-layer insulating film and the second inter-layer insulating film; and

filling up the contact plug holes to form contact plug electrodes.

3. The method according to claim 1 , wherein one of the channel silicon pillars is used as a source-drain-voltage-supply silicon pillar, and the second semiconductor region formed on the top end of the source-drain-voltage-supply silicon pillar is in contact with the first semiconductor region formed on a bottom end of the source-drain-voltage-supply silicon pillar.

4. The method according to claim 2 , wherein the contact plug electrodes comprises:

first contact electrodes connected to the first semiconductor regions;

second contact electrodes connected to the second semiconductor regions through the epitaxial silicon layers; and

third contact electrodes connected to the gate voltage-supply electrodes connected to the gate electrodes.

5. The method according to claim 1 , wherein the capacitance-increase-prevention insulating films are thicker than the gate insulating films.

6. The method according to claim 2 , further comprising forming cylindrical side spacers having holes on the second semiconductor regions before the epitaxial silicon layers are formed.