Power-saving method for Viterbi decoder and bit processing circuit of wireless receiver
View Patent ↗A power-saving method for Viterbi decoder and bit processing circuit of wireless receiver is provided. In response to various computational load of bit processing circuit and/or Viterbi decoder of a wireless receiver, the method is used for adjusting duty cycle of the bit processing circuit and/or the Viterbi decoder so as to save power in addition, in response to various data rates of the wireless receiver, the Viterbi decoder and the bit processing circuit are provided with power based on various duty cycles of related time pulse signals, thereby preventing the Viterbi decoder and/or the bit processing circuit from consuming power while being idle (during time segments of idle operation), so as to reduce power consumption.
1. A power-saving method for Viterbi decoder of a wireless receiver, comprising the steps of:
determining at least one numerical value related to a data rate applied by the wireless receiver while receiving packet; and
deciding a duty cycle of the Viterbi decoder based on the at least one numerical value, wherein power is provided to the Viterbi decoder based on the duty cycle,
wherein the step of determining at least one numerical value is to determine at least one factor among the group of number of bit per subcarrier (N BPSC ), coding rate (R), number of data subcarrier (N SD ), and number of spatial stream (N SS ) applied by the wireless receiver while receiving packet; and the duty cycle is decided based on the at least one factor determined among the group of the number of bit per subcarrier (N BPSC ), the coding rate (R), the number of data subcarrier (N SD ), and number of spatial stream (N SS );
wherein the step of determining at least one numerical value is to calculate a product of at least two of the number of bit per subcarrier (N BPSC ), the coding rate (R), the number of data subcarrier (N SD ), and number of spatial stream (N SS ); and the duty cycle is decided based on the product; and
wherein the step of deciding the duty cycle comprises the steps of:
calculating and producing a maximum product from all possible products of the number of bit per subcarrier (N BPSC ), the coding rate (R), the number of data subcarrier (N SD ), and the number of spatial stream (N SS ); and
calculating a ratio (r) between the product of the at least two of the number of bit per subcarrier (N BPSC ) and the coding rate (R) and the number of data subcarrier (N SD ) and number of spatial stream (N SS ) to the maximum product, and multiplying the ratio (r) with the duty cycle of the wireless receiver, wherein the duty cycle of the Viterbi decoder equals to a product of the ratio (r) and the duty cycle of the wireless receiver.
2. The power-saving method of claim 1 , wherein the step of determining at least one numerical value is to determine a modulation and coding scheme (MCS) adopted by the wireless receiver while receiving packet.
3. The power-saving method of claim 1 , wherein the duty cycle of the Viterbi decoder is greater than or equal to the duty cycle of the wireless receiver.
4. The power-saving method of claim 1 , wherein the wireless receiver is an orthogonal frequency division multiplexing (OFDM) receiver.
5. The power-saving method of claim 1 , wherein the wireless receiver is a code division multiple access (CDMA) receiver.
6. The power-saving method of claim 1 , wherein the wireless receiver is compatible with IEEE 802.11n specifications.
7. A power-saving method for a bit processing circuit of a wireless receiver, wherein the wireless receiver has a time pulse circuit for outputting a time pulse signal, and the time pulse single controls the bit processing circuit to perform bit processing of the wireless receiver, comprising the steps of:
determining a data rate applied by the wireless receiver while receiving packet; and
deciding a duty cycle of the time pulse signal based on the data rate,
wherein power is provided to the bit processing circuit based on the duty cycle of the time pulse signal,
wherein the bit processing circuit comprises a Viterbi decoder for performing Viterbi decoding process, and the method further comprises the steps of:
determining at least one numerical value related to the data rate; and
deciding a duty cycle of the time pulse signal based on the at least one numerical value, and then providing the bit processing circuit with power based on the duty cycle of the time pulse signal;
wherein the step of determining at least one numerical value is to determine at least one factor among the group of number of bit per subcarrier (N BPSC ), coding rate (R), number of data subcarrier (N SD ), and number of spatial stream (N SS ) that are applied by the wireless receiver while receiving packet; and the duty cycle of the time pulse signal is decided based on the determined at least one factor among the group of the number of bit per subcarrier (N BPSC ), the coding rate (R), the number of data subcarrier (N SD ), and the number of spatial stream (N SS );
wherein the step of determining at least one numerical value is to calculate a product of at least two of the number of bit per subcarrier (N BPSC ), the coding rate (R), the number of data subcarrier (N SD ), and number of spatial stream (N SS ), and the duty cycle of the time pulse signal is decided based on the product; and
wherein the step of deciding a duty cycle of time pulse signal further comprises the steps of:
calculating and producing a maximum product from all possible products of the number of bit per subcarrier (N BPSC ), the coding rate (R), the number of data subcarrier (N SD ), and number of spatial stream (N SS ); and
calculating a ratio (r) of the product of the at least two of the number of bit per subcarrier (N BPSC ), coding rate (R) and number of data subcarrier (N SD ) and number of spatial stream (N SS ) to the maximum product, and then calculating a product of the ratio (r) and the duty cycle of the wireless receiver; wherein the duty cycle of the time pulse signal equals to a product of the ratio (r) and the duty cycle of the wireless receiver.
8. The power-saving method for bit processing circuit of wireless receiver of claim 7 , wherein the data rate is determined by modulation and coding scheme (MCS) applied by the wireless receiver while receiving packet.
9. The power-saving method for bit processing circuit of wireless receiver of claim 7 , wherein the duty cycle of the time pulse signal is greater than or equal to the duty cycle of the wireless receiver.
10. The power-saving method for bit processing circuit of wireless receiver of claim 7 , wherein the wireless receiver is an orthogonal frequency division multiplexing (OFDM) receiver.
11. The power-saving method for bit processing circuit of wireless receiver of claim 7 , wherein the wireless receiver is a code division multiple access (CDMA) receiver.
12. The power-saving method for bit processing circuit of wireless receiver of claim 7 , wherein the wireless receiver is compatible with IEEE 802.11n specifications.